[PATCH] D85117: [SVE] Add lowering for fixed length vector and, or & xor operations.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added reviewers: cameron.mcinally, david-arm, sdesmalen.
paulwalker-arm added a comment.

I have mixed feelings out this patch.  Ideally I would like everything lowered to _PRED nodes and then let ISel decide which instruction best does the job.  Unfortunately I could not see a clear way to write a pattern where one of the inputs is ignored.  Am I missing something obvious here? if not then I guess this patch will have to do.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85117/new/

https://reviews.llvm.org/D85117