[PATCH] D85067: [RISCV] Add mucounteren CSR

[Sam Elliott via Phabricator via llvm-commits]

lenary accepted this revision.
lenary added a comment.

LGTM with one minor change. Once we get the LGTM from @jrtc27 and @pzheng, then I'll commit this for you @mmxsrup!



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Comment at: llvm/lib/Target/RISCV/RISCVSystemOperands.td:313
 //===--------------------------
+let AltName = "mucounteren" in
 def : SysReg<"mcountinhibit", 0x320>;
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  https://reviews.llvm.org/D85067/new/

https://reviews.llvm.org/D85067