[PATCH] D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 3 01:34:56 PDT 2020
HsiangKai added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCV.td:152
+ : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
+ "'Zvamo'(Vector AMO Operations)">;
+def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
----------------
Zvamo should imply 'A' extension and 'V' extension.
```
def FeatureExtZvamo
: SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
"'Zvamo'(Vector AMO Operations)",
[FeatureStdExtA, FeatureStdExtV]>;
```
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:945
+
+let Predicates = [HasStdExtV, HasStdExtZvamo, HasStdExtA] in {
+ defm VAMOSWAPEI8 : VAMO<AMOOPVamoSwap, LSWidth8, "vamoswapei8.v">;
----------------
Zvamo should imply 'A' extension and 'V' extension. So, use `HasStdExtZvamo` is enough.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:990
+ defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">;
+} // Predicates = [HasStdExtV, HasStdExtZvamo, HasStdExtA]
----------------
Ditto.
================
Comment at: llvm/test/MC/RISCV/rvv/zvamo.s:1
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+a,experimental-v,experimental-zvamo %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
----------------
`--mattr=+experimental-zvamo` is enough.
================
Comment at: llvm/test/MC/RISCV/rvv/zvamo.s:15
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'V' (Vector Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 0e <unknown>
----------------
instruction requires the following: 'Zvamo'(Vector AMO Operations)
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D85069/new/
https://reviews.llvm.org/D85069
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