[PATCH] D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension
Hsiangkai Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 2 23:58:39 PDT 2020
HsiangKai added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:949
+ defm VAMOSWAPEI32 : VAMO<AMOOPVamoSwap, LSWidth32, "vamoswapei32.v">;
+ defm VAMOSWAPEI64 : VAMO<AMOOPVamoSwap, LSWidth64, "vamoswapei64.v">;
+
----------------
"If index EEW is greater than XLEN, an illegal instruction exception is raised."
We could collect all AMO instructions with EEW = 64 into one place and use "Predicates = [IsRV64]" to ensure XLEN >= EEW.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D85069/new/
https://reviews.llvm.org/D85069
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