[llvm] a96921a - [RISCV] eliminate the repetition declare of SDLoc DL

[via llvm-commits]

Author: StephenFan
Date: 2020-08-03T10:24:30+08:00
New Revision: a96921afa7024533cf451ef13708082876233eef

URL: https://github.com/llvm/llvm-project/commit/a96921afa7024533cf451ef13708082876233eef
DIFF: https://github.com/llvm/llvm-project/commit/a96921afa7024533cf451ef13708082876233eef.diff

LOG: [RISCV] eliminate the repetition declare of SDLoc DL

Differential revision: https://reviews.llvm.org/D85002

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cad5f8e21185..773a09869033 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1003,7 +1003,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::BITCAST: {
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            Subtarget.hasStdExtF() && "Unexpected custom legalisation");
-    SDLoc DL(N);
     SDValue Op0 = N->getOperand(0);
     if (Op0.getValueType() != MVT::f32)
       return;