[PATCH] D85101: [AArch64][CodeGen] Restrict bfloat vector operations to what's actually supported

[Ties Stuij via Phabricator via llvm-commits]

stuij created this revision.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
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stuij requested review of this revision.

Previously in addTypeForNeon, we would set the operations for bfloat vectors
like other generic types. But as bfloat is a storage-only type a number of
operations shouldn't be set. This patch fixes that.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85101

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
  llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll


Index: llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
===================================================================
--- llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
+++ llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
 
 ; bfloat16x4_t test_vcreate_bf16(uint64_t a) { return vcreate_bf16(a); }
 define <4 x bfloat> @test_vcreate_bf16(i64 %a) nounwind {
Index: llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
===================================================================
--- llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
+++ llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi | FileCheck %s
+; RUN: llc < %s -asm-verbose=0 -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
 
 define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_v4i16:
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -161,7 +161,8 @@
     addDRTypeForNEON(MVT::v1i64);
     addDRTypeForNEON(MVT::v1f64);
     addDRTypeForNEON(MVT::v4f16);
-    addDRTypeForNEON(MVT::v4bf16);
+    if (Subtarget->hasBF16())
+      addDRTypeForNEON(MVT::v4bf16);
 
     addQRTypeForNEON(MVT::v4f32);
     addQRTypeForNEON(MVT::v2f64);
@@ -170,7 +171,8 @@
     addQRTypeForNEON(MVT::v4i32);
     addQRTypeForNEON(MVT::v2i64);
     addQRTypeForNEON(MVT::v8f16);
-    addQRTypeForNEON(MVT::v8bf16);
+    if (Subtarget->hasBF16())
+      addQRTypeForNEON(MVT::v8bf16);
   }
 
   if (Subtarget->hasSVE()) {
@@ -1014,10 +1016,14 @@
   setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
   setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
-  setOperationAction(ISD::SRA, VT, Custom);
-  setOperationAction(ISD::SRL, VT, Custom);
-  setOperationAction(ISD::SHL, VT, Custom);
-  setOperationAction(ISD::OR, VT, Custom);
+
+  if (VT.getVectorElementType() != MVT::bf16) {
+    setOperationAction(ISD::SRA, VT, Custom);
+    setOperationAction(ISD::SRL, VT, Custom);
+    setOperationAction(ISD::SHL, VT, Custom);
+    setOperationAction(ISD::OR, VT, Custom);
+  }
+
   setOperationAction(ISD::SETCC, VT, Custom);
   setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
 
@@ -1031,11 +1037,13 @@
   if (VT != MVT::v8i8 && VT != MVT::v16i8)
     setOperationAction(ISD::CTPOP, VT, Custom);
 
-  setOperationAction(ISD::UDIV, VT, Expand);
-  setOperationAction(ISD::SDIV, VT, Expand);
-  setOperationAction(ISD::UREM, VT, Expand);
-  setOperationAction(ISD::SREM, VT, Expand);
-  setOperationAction(ISD::FREM, VT, Expand);
+  if (VT.getVectorElementType() != MVT::bf16) {
+    setOperationAction(ISD::UDIV, VT, Expand);
+    setOperationAction(ISD::SDIV, VT, Expand);
+    setOperationAction(ISD::UREM, VT, Expand);
+    setOperationAction(ISD::SREM, VT, Expand);
+    setOperationAction(ISD::FREM, VT, Expand);
+  }
 
   setOperationAction(ISD::FP_TO_SINT, VT, Custom);
   setOperationAction(ISD::FP_TO_UINT, VT, Custom);
@@ -1050,6 +1058,7 @@
 
   // F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
   if (VT.isFloatingPoint() &&
+      VT.getVectorElementType() != MVT::bf16 &&
       (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
     for (unsigned Opcode :
          {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})


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