[llvm] bb13c34 - [X86][AVX] Ensure we only combine to PSHUFLW/PSHUFHW on supporting targets

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-08-01T19:18:11+01:00
New Revision: bb13c34c3aa100006461c972319abfef0af70603

URL: https://github.com/llvm/llvm-project/commit/bb13c34c3aa100006461c972319abfef0af70603
DIFF: https://github.com/llvm/llvm-project/commit/bb13c34c3aa100006461c972319abfef0af70603.diff

LOG: [X86][AVX] Ensure we only combine to PSHUFLW/PSHUFHW on supporting targets

Noticed while investigating combining from concatenated shuffle vectors, we weren't checking that PSHUFLW/PSHUFHW was legal - we were depending on lowering splitting to subvectors.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d628cdfc1fdf..b89502dc7020 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34146,7 +34146,10 @@ static bool matchUnaryPermuteShuffle(MVT MaskVT, ArrayRef<int> Mask,
   }
 
   // Handle PSHUFLW/PSHUFHW vXi16 repeated patterns.
-  if (!ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == 16) {
+  if (!ContainsZeros && AllowIntDomain && MaskScalarSizeInBits == 16 &&
+      ((MaskVT.is128BitVector() && Subtarget.hasSSE2()) ||
+       (MaskVT.is256BitVector() && Subtarget.hasAVX2()) ||
+       (MaskVT.is512BitVector() && Subtarget.hasBWI()))) {
     SmallVector<int, 4> RepeatedMask;
     if (is128BitLaneRepeatedShuffleMask(MaskEltVT, Mask, RepeatedMask)) {
       ArrayRef<int> LoMask(RepeatedMask.data() + 0, 4);