[llvm] 605fd4d - [VE] Change calling convention to follow ABI
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 18:09:03 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-08-01T10:08:54+09:00
New Revision: 605fd4d77ce19c4d8c331732b490ef436ab093c2
URL: https://github.com/llvm/llvm-project/commit/605fd4d77ce19c4d8c331732b490ef436ab093c2
DIFF: https://github.com/llvm/llvm-project/commit/605fd4d77ce19c4d8c331732b490ef436ab093c2.diff
LOG: [VE] Change calling convention to follow ABI
Change to expand all arguments and return values to i64 to follow ABI.
Update regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D84581
Added:
Modified:
llvm/lib/Target/VE/VECallingConv.td
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/test/CodeGen/VE/addition.ll
llvm/test/CodeGen/VE/bitcast.ll
llvm/test/CodeGen/VE/bitreverse.ll
llvm/test/CodeGen/VE/branch1.ll
llvm/test/CodeGen/VE/bswap.ll
llvm/test/CodeGen/VE/call.ll
llvm/test/CodeGen/VE/cast.ll
llvm/test/CodeGen/VE/constants.ll
llvm/test/CodeGen/VE/ctlz.ll
llvm/test/CodeGen/VE/ctpop.ll
llvm/test/CodeGen/VE/cttz.ll
llvm/test/CodeGen/VE/div.ll
llvm/test/CodeGen/VE/fp_to_int.ll
llvm/test/CodeGen/VE/int_to_fp.ll
llvm/test/CodeGen/VE/left_shift.ll
llvm/test/CodeGen/VE/load_off.ll
llvm/test/CodeGen/VE/max.ll
llvm/test/CodeGen/VE/min.ll
llvm/test/CodeGen/VE/multiply.ll
llvm/test/CodeGen/VE/nnd.ll
llvm/test/CodeGen/VE/or.ll
llvm/test/CodeGen/VE/pic_access_static_data.ll
llvm/test/CodeGen/VE/rem.ll
llvm/test/CodeGen/VE/right_shift.ll
llvm/test/CodeGen/VE/rotl.ll
llvm/test/CodeGen/VE/rotr.ll
llvm/test/CodeGen/VE/select.ll
llvm/test/CodeGen/VE/selectccf32.ll
llvm/test/CodeGen/VE/selectccf32c.ll
llvm/test/CodeGen/VE/selectccf32i.ll
llvm/test/CodeGen/VE/selectccf64c.ll
llvm/test/CodeGen/VE/selectcci32.ll
llvm/test/CodeGen/VE/selectcci32c.ll
llvm/test/CodeGen/VE/selectcci32i.ll
llvm/test/CodeGen/VE/selectcci64c.ll
llvm/test/CodeGen/VE/setccf32.ll
llvm/test/CodeGen/VE/setccf32i.ll
llvm/test/CodeGen/VE/setccf64.ll
llvm/test/CodeGen/VE/setccf64i.ll
llvm/test/CodeGen/VE/setcci32.ll
llvm/test/CodeGen/VE/setcci32i.ll
llvm/test/CodeGen/VE/setcci64.ll
llvm/test/CodeGen/VE/setcci64i.ll
llvm/test/CodeGen/VE/sext_zext_load.ll
llvm/test/CodeGen/VE/subtraction.ll
llvm/test/CodeGen/VE/truncstore.ll
llvm/test/CodeGen/VE/va_caller.ll
llvm/test/CodeGen/VE/xor.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VECallingConv.td b/llvm/lib/Target/VE/VECallingConv.td
index 4f04dae884ab..acdae68323fd 100644
--- a/llvm/lib/Target/VE/VECallingConv.td
+++ b/llvm/lib/Target/VE/VECallingConv.td
@@ -14,13 +14,6 @@
// Aurora VE
//===----------------------------------------------------------------------===//
def CC_VE_C_Stack: CallingConv<[
- // float --> need special handling like below.
- // 0 4
- // +------+------+
- // | empty| float|
- // +------+------+
- CCIfType<[f32], CCCustom<"allocateFloat">>,
-
// All of the rest are assigned to the stack in 8-byte aligned units.
CCAssignToStack<0, 8>
]>;
@@ -28,20 +21,18 @@ def CC_VE_C_Stack: CallingConv<[
def CC_VE : CallingConv<[
// All arguments get passed in generic registers if there is space.
- // Promote i1/i8/i16 arguments to i32.
- CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+ // Promote i1/i8/i16/i32 arguments to i64.
+ CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
- // bool, char, int, enum, long --> generic integer 32 bit registers
- CCIfType<[i32], CCAssignToRegWithShadow<
- [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],
- [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
-
- // float --> generic floating point 32 bit registers
- CCIfType<[f32], CCAssignToRegWithShadow<
- [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],
- [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
+ // Convert float arguments to i64 with padding.
+ // 63 31 0
+ // +------+------+
+ // | float| 0 |
+ // +------+------+
+ CCIfType<[f32], CCBitConvertToType<i64>>,
- // long long/double --> generic 64 bit registers
+ // bool, char, int, enum, long, long long, float, double
+ // --> generic 64 bit registers
CCIfType<[i64, f64],
CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
@@ -52,31 +43,32 @@ def CC_VE : CallingConv<[
// All arguments get passed in stack for varargs function or non-prototyped
// function.
def CC_VE2 : CallingConv<[
- // float --> need special handling like below.
- // 0 4
+ // Promote i1/i8/i16/i32 arguments to i64.
+ CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
+
+ // Convert float arguments to i64 with padding.
+ // 63 31 0
// +------+------+
- // | empty| float|
+ // | float| 0 |
// +------+------+
- CCIfType<[f32], CCCustom<"allocateFloat">>,
+ CCIfType<[f32], CCBitConvertToType<i64>>,
CCAssignToStack<0, 8>
]>;
def RetCC_VE : CallingConv<[
- // Promote i1/i8/i16 arguments to i32.
- CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
-
- // bool, char, int, enum, long --> generic integer 32 bit registers
- CCIfType<[i32], CCAssignToRegWithShadow<
- [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],
- [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
+ // Promote i1/i8/i16/i32 return values to i64.
+ CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
- // float --> generic floating point 32 bit registers
- CCIfType<[f32], CCAssignToRegWithShadow<
- [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],
- [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
+ // Convert float return values to i64 with padding.
+ // 63 31 0
+ // +------+------+
+ // | float| 0 |
+ // +------+------+
+ CCIfType<[f32], CCBitConvertToType<i64>>,
- // long long/double --> generic 64 bit registers
+ // bool, char, int, enum, long, long long, float, double
+ // --> generic 64 bit registers
CCIfType<[i64, f64],
CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
]>;
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index ab720545dd83..e2232f4500e3 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -38,28 +38,6 @@ using namespace llvm;
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
-static bool allocateFloat(unsigned ValNo, MVT ValVT, MVT LocVT,
- CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State) {
- switch (LocVT.SimpleTy) {
- case MVT::f32: {
- // Allocate stack like below
- // 0 4
- // +------+------+
- // | empty| float|
- // +------+------+
- // Use align=8 for dummy area to align the beginning of these 2 area.
- State.AllocateStack(4, Align(8)); // for empty area
- // Use align=4 for value to place it at just after the dummy area.
- unsigned Offset = State.AllocateStack(4, Align(4)); // for float value area
- State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
- return true;
- }
- default:
- return false;
- }
-}
-
#include "VEGenCallingConv.inc"
bool VETargetLowering::CanLowerReturn(
@@ -109,6 +87,22 @@ VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
case CCValAssign::AExt:
OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
break;
+ case CCValAssign::BCvt: {
+ // Convert a float return value to i64 with padding.
+ // 63 31 0
+ // +------+------+
+ // | float| 0 |
+ // +------+------+
+ assert(VA.getLocVT() == MVT::i64);
+ assert(VA.getValVT() == MVT::f32);
+ SDValue Undef = SDValue(
+ DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
+ SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
+ OutVal = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
+ MVT::i64, Undef, OutVal, Sub_f32),
+ 0);
+ break;
+ }
default:
llvm_unreachable("Unknown loc info!");
}
@@ -179,6 +173,20 @@ SDValue VETargetLowering::LowerFormalArguments(
Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
DAG.getValueType(VA.getValVT()));
break;
+ case CCValAssign::BCvt: {
+ // Extract a float argument from i64 with padding.
+ // 63 31 0
+ // +------+------+
+ // | float| 0 |
+ // +------+------+
+ assert(VA.getLocVT() == MVT::i64);
+ assert(VA.getValVT() == MVT::f32);
+ SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
+ Arg = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
+ MVT::f32, Arg, Sub_f32),
+ 0);
+ break;
+ }
default:
break;
}
@@ -197,6 +205,20 @@ SDValue VETargetLowering::LowerFormalArguments(
// beginning of the arguments area at %fp+176.
unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;
unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
+
+ // Adjust offset for a float argument by adding 4 since the argument is
+ // stored in 8 bytes buffer with offset like below. LLVM generates
+ // 4 bytes load instruction, so need to adjust offset here. This
+ // adjustment is required in only LowerFormalArguments. In LowerCall,
+ // a float argument is converted to i64 first, and stored as 8 bytes
+ // data, which is required by ABI, so no need for adjustment.
+ // 0 4
+ // +------+------+
+ // | empty| float|
+ // +------+------+
+ if (VA.getValVT() == MVT::f32)
+ Offset += 4;
+
int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
InVals.push_back(
DAG.getLoad(VA.getValVT(), DL, Chain,
@@ -371,6 +393,22 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
case CCValAssign::AExt:
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
break;
+ case CCValAssign::BCvt: {
+ // Convert a float argument to i64 with padding.
+ // 63 31 0
+ // +------+------+
+ // | float| 0 |
+ // +------+------+
+ assert(VA.getLocVT() == MVT::i64);
+ assert(VA.getValVT() == MVT::f32);
+ SDValue Undef = SDValue(
+ DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
+ SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
+ Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
+ MVT::i64, Undef, Arg, Sub_f32),
+ 0);
+ break;
+ }
}
if (VA.isRegLoc()) {
@@ -488,6 +526,20 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
DAG.getValueType(VA.getValVT()));
break;
+ case CCValAssign::BCvt: {
+ // Extract a float return value from i64 with padding.
+ // 63 31 0
+ // +------+------+
+ // | float| 0 |
+ // +------+------+
+ assert(VA.getLocVT() == MVT::i64);
+ assert(VA.getValVT() == MVT::f32);
+ SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
+ RV = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
+ MVT::f32, RV, Sub_f32),
+ 0);
+ break;
+ }
default:
break;
}
diff --git a/llvm/test/CodeGen/VE/addition.ll b/llvm/test/CodeGen/VE/addition.ll
index 730776ec534b..54275e9e0e26 100644
--- a/llvm/test/CodeGen/VE/addition.ll
+++ b/llvm/test/CodeGen/VE/addition.ll
@@ -3,9 +3,11 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i8 %1, %0
ret i8 %3
@@ -14,9 +16,11 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i16 %1, %0
ret i16 %3
@@ -25,6 +29,8 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i32 %1, %0
@@ -43,6 +49,8 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -53,6 +61,8 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -63,6 +73,8 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i32 %1, %0
@@ -81,9 +93,10 @@ define i64 @func9(i64 %0, i64 %1) {
define signext i8 @func13(i8 signext %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%2 = add i8 %0, 5
ret i8 %2
@@ -92,9 +105,10 @@ define signext i8 @func13(i8 signext %0) {
define signext i16 @func14(i16 signext %0) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%2 = add i16 %0, 5
ret i16 %2
@@ -103,6 +117,7 @@ define signext i16 @func14(i16 signext %0) {
define i32 @func15(i32 %0) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i32 %0, 5
@@ -121,6 +136,7 @@ define i64 @func16(i64 %0) {
define zeroext i8 @func18(i8 zeroext %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -131,6 +147,7 @@ define zeroext i8 @func18(i8 zeroext %0) {
define zeroext i16 @func19(i16 zeroext %0) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -141,6 +158,7 @@ define zeroext i16 @func19(i16 zeroext %0) {
define i32 @func20(i32 %0) {
; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%2 = add i32 %0, 5
diff --git a/llvm/test/CodeGen/VE/bitcast.ll b/llvm/test/CodeGen/VE/bitcast.ll
index dacc8f189e96..d7c09cd46b61 100644
--- a/llvm/test/CodeGen/VE/bitcast.ll
+++ b/llvm/test/CodeGen/VE/bitcast.ll
@@ -22,9 +22,8 @@ define dso_local double @bitcastl2d(i64 %x) {
define dso_local float @bitcastw2f(i32 %x) {
; CHECK-LABEL: bitcastw2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sll %s0, %s0, 32
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = bitcast i32 %x to float
ret float %r
@@ -34,9 +33,7 @@ define dso_local float @bitcastw2f(i32 %x) {
define dso_local i32 @bitcastf2w(float %x) {
; CHECK-LABEL: bitcastf2w:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0
; CHECK-NEXT: sra.l %s0, %s0, 32
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = bitcast float %x to i32
ret i32 %r
diff --git a/llvm/test/CodeGen/VE/bitreverse.ll b/llvm/test/CodeGen/VE/bitreverse.ll
index fce969af657e..af58afe38fd9 100644
--- a/llvm/test/CodeGen/VE/bitreverse.ll
+++ b/llvm/test/CodeGen/VE/bitreverse.ll
@@ -14,10 +14,8 @@ declare i64 @llvm.bitreverse.i64(i64)
define i32 @func2(i32 %p) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 32
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.bitreverse.i32(i32 %p)
ret i32 %r
@@ -28,10 +26,8 @@ declare i32 @llvm.bitreverse.i32(i32)
define signext i16 @func3(i16 signext %p) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.bitreverse.i16(i16 %p)
ret i16 %r
@@ -42,10 +38,8 @@ declare i16 @llvm.bitreverse.i16(i16)
define signext i8 @func4(i8 signext %p) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i8 @llvm.bitreverse.i8(i8 %p)
ret i8 %r
@@ -65,10 +59,8 @@ define i64 @func5(i64 %p) {
define i32 @func6(i32 %p) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 32
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.bitreverse.i32(i32 %p)
ret i32 %r
@@ -77,10 +69,8 @@ define i32 @func6(i32 %p) {
define zeroext i16 @func7(i16 zeroext %p) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 48
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.bitreverse.i16(i16 %p)
ret i16 %r
@@ -89,10 +79,8 @@ define zeroext i16 @func7(i16 zeroext %p) {
define zeroext i8 @func8(i8 zeroext %p) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
; CHECK-NEXT: brv %s0, %s0
; CHECK-NEXT: srl %s0, %s0, 56
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i8 @llvm.bitreverse.i8(i8 %p)
ret i8 %r
diff --git a/llvm/test/CodeGen/VE/branch1.ll b/llvm/test/CodeGen/VE/branch1.ll
index c9f0a22c4c0a..5561284c992e 100644
--- a/llvm/test/CodeGen/VE/branch1.ll
+++ b/llvm/test/CodeGen/VE/branch1.ll
@@ -3,19 +3,22 @@
define signext i8 @func1(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.w %s0, %s1, .LBB0_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB0_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp sgt i8 %a, %b
@@ -36,17 +39,20 @@ declare i32 @ret(i32)
define i32 @func2(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.w %s0, %s1, .LBB1_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB1_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp sgt i16 %a, %b
@@ -64,17 +70,20 @@ join:
define i32 @func3(i32 %a, i32 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.w %s0, %s1, .LBB2_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB2_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp sgt i32 %a, %b
@@ -92,17 +101,18 @@ join:
define i32 @func4(i64 %a, i64 %b) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.l %s0, %s1, .LBB3_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brle.l %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB3_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp sgt i64 %a, %b
@@ -120,18 +130,21 @@ join:
define i32 @func5(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_5:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brle.w 0, %s0, .LBB4_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB4_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp ugt i8 %a, %b
@@ -149,18 +162,21 @@ join:
define i32 @func6(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_5:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brle.w 0, %s0, .LBB5_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB5_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp ugt i16 %a, %b
@@ -178,18 +194,21 @@ join:
define i32 @func7(i32 %a, i32 %b) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_5:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brle.w 0, %s0, .LBB6_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB6_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = icmp ugt i32 %a, %b
@@ -207,17 +226,18 @@ join:
define i32 @func8(float %a, float %b) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brlenan.s %s0, %s1, .LBB7_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brlenan.s %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB7_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = fcmp ogt float %a, %b
@@ -235,17 +255,18 @@ join:
define i32 @func9(double %a, double %b) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brlenan.d %s0, %s1, .LBB8_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brlenan.d %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB8_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = fcmp ogt double %a, %b
@@ -264,17 +285,18 @@ define i32 @func10(double %a, double %b) {
; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_5:
; CHECK-NEXT: lea.sl %s1, 1075052544
-; CHECK-NEXT: brlenan.d %s0, %s1, .LBB9_1
-; CHECK-NEXT: # %bb.2:
+; CHECK-NEXT: brlenan.d %s0, %s1, .LBB{{[0-9]+}}_1
+; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
; CHECK-NEXT: or %s0, 2, (0)1
; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: br.l.t .LBB9_3
-; CHECK: .LBB{{[0-9]+}}_1:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
; CHECK-NEXT: or %s11, 0, %s9
entry:
%cmp = fcmp ogt double %a, 5.000000e+00
diff --git a/llvm/test/CodeGen/VE/bswap.ll b/llvm/test/CodeGen/VE/bswap.ll
index 274085462856..39569d8889c5 100644
--- a/llvm/test/CodeGen/VE/bswap.ll
+++ b/llvm/test/CodeGen/VE/bswap.ll
@@ -14,9 +14,8 @@ declare i64 @llvm.bswap.i64(i64)
define i32 @func2(i32 %p) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.bswap.i32(i32 %p)
ret i32 %r
@@ -27,9 +26,12 @@ declare i32 @llvm.bswap.i32(i32)
define signext i16 @func3(i16 signext %p) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: and %s0, %s0, (32)0
+; CHECK-NEXT: srl %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.bswap.i16(i16 %p)
ret i16 %r
@@ -49,9 +51,8 @@ define i64 @func4(i64 %p) {
define i32 @func5(i32 %p) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.bswap.i32(i32 %p)
ret i32 %r
@@ -60,11 +61,11 @@ define i32 @func5(i32 %p) {
define zeroext i16 @func6(i16 zeroext %p) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.bswap.i16(i16 %p)
ret i16 %r
diff --git a/llvm/test/CodeGen/VE/call.ll b/llvm/test/CodeGen/VE/call.ll
index 9e9f22b6d823..386a5fd74bf9 100644
--- a/llvm/test/CodeGen/VE/call.ll
+++ b/llvm/test/CodeGen/VE/call.ll
@@ -20,7 +20,7 @@ define i32 @stack_call_int() {
; CHECK-LABEL: stack_call_int:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 10, (0)1
-; CHECK-NEXT: stl %s0, 248(, %s11)
+; CHECK-NEXT: st %s0, 248(, %s11)
; CHECK-NEXT: or %s34, 9, (0)1
; CHECK-NEXT: lea %s0, stack_callee_int at lo
; CHECK-NEXT: and %s0, %s0, (32)0
@@ -33,7 +33,7 @@ define i32 @stack_call_int() {
; CHECK-NEXT: or %s5, 6, (0)1
; CHECK-NEXT: or %s6, 7, (0)1
; CHECK-NEXT: or %s7, 8, (0)1
-; CHECK-NEXT: stl %s34, 240(, %s11)
+; CHECK-NEXT: st %s34, 240(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @stack_callee_int(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10)
@@ -46,7 +46,7 @@ define i32 @stack_call_int_szext() {
; CHECK-LABEL: stack_call_int_szext:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, -1, (0)1
-; CHECK-NEXT: stl %s0, 248(, %s11)
+; CHECK-NEXT: st %s0, 248(, %s11)
; CHECK-NEXT: lea %s34, 65535
; CHECK-NEXT: lea %s1, stack_callee_int_szext at lo
; CHECK-NEXT: and %s1, %s1, (32)0
@@ -58,7 +58,7 @@ define i32 @stack_call_int_szext() {
; CHECK-NEXT: or %s5, 6, (0)1
; CHECK-NEXT: or %s6, 7, (0)1
; CHECK-NEXT: or %s7, 8, (0)1
-; CHECK-NEXT: stl %s34, 240(, %s11)
+; CHECK-NEXT: st %s34, 240(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @stack_callee_int_szext(i1 -1, i8 -1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i16 -1, i8 -1)
@@ -70,12 +70,9 @@ declare i32 @stack_callee_int_szext(i1 signext, i8 zeroext, i32, i32, i32, i32,
define float @stack_call_float() {
; CHECK-LABEL: stack_call_float:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: lea %s0, 1092616192
-; CHECK-NEXT: stl %s0, 252(, %s11)
-; CHECK-NEXT: lea %s34, 1091567616
-; CHECK-NEXT: lea %s0, stack_callee_float at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, stack_callee_float at hi(, %s0)
+; CHECK-NEXT: lea.sl %s0, 1092616192
+; CHECK-NEXT: st %s0, 248(, %s11)
+; CHECK-NEXT: lea.sl %s34, 1091567616
; CHECK-NEXT: lea.sl %s0, 1065353216
; CHECK-NEXT: lea.sl %s1, 1073741824
; CHECK-NEXT: lea.sl %s2, 1077936128
@@ -84,15 +81,10 @@ define float @stack_call_float() {
; CHECK-NEXT: lea.sl %s5, 1086324736
; CHECK-NEXT: lea.sl %s6, 1088421888
; CHECK-NEXT: lea.sl %s7, 1090519040
-; CHECK-NEXT: stl %s34, 244(, %s11)
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 killed $sx0
-; CHECK-NEXT: # kill: def $sf1 killed $sf1 killed $sx1
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 killed $sx2
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 killed $sx3
-; CHECK-NEXT: # kill: def $sf4 killed $sf4 killed $sx4
-; CHECK-NEXT: # kill: def $sf5 killed $sf5 killed $sx5
-; CHECK-NEXT: # kill: def $sf6 killed $sf6 killed $sx6
-; CHECK-NEXT: # kill: def $sf7 killed $sf7 killed $sx7
+; CHECK-NEXT: lea %s35, stack_callee_float at lo
+; CHECK-NEXT: and %s35, %s35, (32)0
+; CHECK-NEXT: lea.sl %s12, stack_callee_float at hi(, %s35)
+; CHECK-NEXT: st %s34, 240(, %s11)
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call float @stack_callee_float(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0)
@@ -104,11 +96,11 @@ declare float @stack_callee_float(float, float, float, float, float, float, floa
define float @stack_call_float2(float %p0) {
; CHECK-LABEL: stack_call_float2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: stu %s0, 252(, %s11)
+; CHECK-NEXT: st %s0, 248(, %s11)
; CHECK-NEXT: lea %s1, stack_callee_float at lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s12, stack_callee_float at hi(, %s1)
-; CHECK-NEXT: stu %s0, 244(, %s11)
+; CHECK-NEXT: st %s0, 240(, %s11)
; CHECK-NEXT: or %s1, 0, %s0
; CHECK-NEXT: or %s2, 0, %s0
; CHECK-NEXT: or %s3, 0, %s0
diff --git a/llvm/test/CodeGen/VE/cast.ll b/llvm/test/CodeGen/VE/cast.ll
index 51126e123ac6..07ad969a1bd3 100644
--- a/llvm/test/CodeGen/VE/cast.ll
+++ b/llvm/test/CodeGen/VE/cast.ll
@@ -4,6 +4,7 @@ define i32 @i() {
; CHECK-LABEL: i:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, -2147483648
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
ret i32 -2147483648
}
@@ -12,6 +13,7 @@ define i32 @ui() {
; CHECK-LABEL: ui:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s0, -2147483648
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
ret i32 -2147483648
}
@@ -37,6 +39,7 @@ define signext i8 @d2c(double %x) {
; CHECK-LABEL: d2c:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptosi double %x to i8
ret i8 %r
@@ -46,6 +49,7 @@ define zeroext i8 @d2uc(double %x) {
; CHECK-LABEL: d2uc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptoui double %x to i8
ret i8 %r
@@ -55,6 +59,7 @@ define signext i16 @d2s(double %x) {
; CHECK-LABEL: d2s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptosi double %x to i16
ret i16 %r
@@ -64,6 +69,7 @@ define zeroext i16 @d2us(double %x) {
; CHECK-LABEL: d2us:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptoui double %x to i16
ret i16 %r
@@ -82,7 +88,6 @@ define i32 @d2ui(double %x) {
; CHECK-LABEL: d2ui:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptoui double %x to i32
ret i32 %r
@@ -133,6 +138,7 @@ define signext i8 @f2c(float %x) {
; CHECK-LABEL: f2c:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptosi float %x to i8
ret i8 %r
@@ -142,6 +148,7 @@ define zeroext i8 @f2uc(float %x) {
; CHECK-LABEL: f2uc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptoui float %x to i8
ret i8 %r
@@ -151,6 +158,7 @@ define signext i16 @f2s(float %x) {
; CHECK-LABEL: f2s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptosi float %x to i16
ret i16 %r
@@ -160,6 +168,7 @@ define zeroext i16 @f2us(float %x) {
; CHECK-LABEL: f2us:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptoui float %x to i16
ret i16 %r
@@ -179,7 +188,6 @@ define i32 @f2ui(float %x) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = fptoui float %x to i32
ret i32 %r
@@ -234,7 +242,6 @@ define signext i8 @ll2c(i64 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i8
ret i8 %2
@@ -254,7 +261,6 @@ define signext i16 @ll2s(i64 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i16
ret i16 %2
@@ -272,7 +278,6 @@ define zeroext i16 @ll2us(i64 %0) {
define i32 @ll2i(i64 %0) {
; CHECK-LABEL: ll2i:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i32
ret i32 %2
@@ -281,7 +286,6 @@ define i32 @ll2i(i64 %0) {
define i32 @ll2ui(i64 %0) {
; CHECK-LABEL: ll2ui:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i32
ret i32 %2
@@ -325,7 +329,6 @@ define signext i8 @ull2c(i64 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i8
ret i8 %2
@@ -345,7 +348,6 @@ define signext i16 @ull2s(i64 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i16
ret i16 %2
@@ -363,7 +365,6 @@ define zeroext i16 @ull2us(i64 %0) {
define i32 @ull2i(i64 %0) {
; CHECK-LABEL: ull2i:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i32
ret i32 %2
@@ -372,7 +373,6 @@ define i32 @ull2i(i64 %0) {
define i32 @ull2ui(i64 %0) {
; CHECK-LABEL: ull2ui:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i64 %0 to i32
ret i32 %2
@@ -433,8 +433,8 @@ define double @ull2d(i64 %x) {
define signext i8 @i2c(i32 %0) {
; CHECK-LABEL: i2c:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i32 %0 to i8
ret i8 %2
@@ -452,8 +452,8 @@ define zeroext i8 @i2uc(i32 %0) {
define signext i16 @i2s(i32 %0) {
; CHECK-LABEL: i2s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i32 %0 to i16
ret i16 %2
@@ -503,6 +503,7 @@ define i64 @i2ull(i32 %0) {
define float @i2f(i32 %x) {
; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i32 %x to float
@@ -512,6 +513,7 @@ define float @i2f(i32 %x) {
define double @i2d(i32 %x) {
; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i32 %x to double
@@ -521,8 +523,8 @@ define double @i2d(i32 %x) {
define signext i8 @ui2c(i32 %0) {
; CHECK-LABEL: ui2c:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i32 %0 to i8
ret i8 %2
@@ -540,8 +542,8 @@ define zeroext i8 @ui2uc(i32 %0) {
define signext i16 @ui2s(i32 %0) {
; CHECK-LABEL: ui2s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i32 %0 to i16
ret i16 %2
@@ -573,7 +575,7 @@ define i32 @ui2ui(i32 returned %0) {
define i64 @ui2ll(i32 %0) {
; CHECK-LABEL: ui2ll:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i32 %0 to i64
ret i64 %2
@@ -582,7 +584,7 @@ define i64 @ui2ll(i32 %0) {
define i64 @ui2ull(i32 %0) {
; CHECK-LABEL: ui2ull:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i32 %0 to i64
ret i64 %2
@@ -591,7 +593,7 @@ define i64 @ui2ull(i32 %0) {
define float @ui2f(i32 %x) {
; CHECK-LABEL: ui2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
@@ -602,7 +604,7 @@ define float @ui2f(i32 %x) {
define double @ui2d(i32 %x) {
; CHECK-LABEL: ui2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i32 %x to double
@@ -612,8 +614,8 @@ define double @ui2d(i32 %x) {
define signext i8 @s2c(i16 signext %0) {
; CHECK-LABEL: s2c:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i16 %0 to i8
ret i8 %2
@@ -662,7 +664,6 @@ define i32 @s2ui(i16 signext %0) {
define i64 @s2ll(i16 signext %0) {
; CHECK-LABEL: s2ll:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i16 %0 to i64
ret i64 %2
@@ -671,7 +672,6 @@ define i64 @s2ll(i16 signext %0) {
define i64 @s2ull(i16 signext %0) {
; CHECK-LABEL: s2ull:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i16 %0 to i64
ret i64 %2
@@ -680,6 +680,7 @@ define i64 @s2ull(i16 signext %0) {
define float @s2f(i16 signext %x) {
; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i16 %x to float
@@ -689,6 +690,7 @@ define float @s2f(i16 signext %x) {
define double @s2d(i16 signext %x) {
; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i16 %x to double
@@ -698,8 +700,8 @@ define double @s2d(i16 signext %x) {
define signext i8 @us2c(i16 zeroext %0) {
; CHECK-LABEL: us2c:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i16 %0 to i8
ret i8 %2
@@ -717,8 +719,8 @@ define zeroext i8 @us2uc(i16 zeroext %0) {
define signext i16 @us2s(i16 returned zeroext %0) {
; CHECK-LABEL: us2s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
ret i16 %0
}
@@ -749,7 +751,6 @@ define i32 @us2ui(i16 zeroext %0) {
define i64 @us2ll(i16 zeroext %0) {
; CHECK-LABEL: us2ll:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i16 %0 to i64
ret i64 %2
@@ -758,7 +759,6 @@ define i64 @us2ll(i16 zeroext %0) {
define i64 @us2ull(i16 zeroext %0) {
; CHECK-LABEL: us2ull:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i16 %0 to i64
ret i64 %2
@@ -767,6 +767,7 @@ define i64 @us2ull(i16 zeroext %0) {
define float @us2f(i16 zeroext %x) {
; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i16 %x to float
@@ -776,6 +777,7 @@ define float @us2f(i16 zeroext %x) {
define double @us2d(i16 zeroext %x) {
; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i16 %x to double
@@ -833,7 +835,6 @@ define i32 @c2ui(i8 signext %0) {
define i64 @c2ll(i8 signext %0) {
; CHECK-LABEL: c2ll:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i8 %0 to i64
ret i64 %2
@@ -842,7 +843,6 @@ define i64 @c2ll(i8 signext %0) {
define i64 @c2ull(i8 signext %0) {
; CHECK-LABEL: c2ull:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i8 %0 to i64
ret i64 %2
@@ -851,6 +851,7 @@ define i64 @c2ull(i8 signext %0) {
define float @c2f(i8 signext %x) {
; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i8 %x to float
@@ -860,6 +861,7 @@ define float @c2f(i8 signext %x) {
define double @c2d(i8 signext %x) {
; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i8 %x to double
@@ -869,8 +871,8 @@ define double @c2d(i8 signext %x) {
define signext i8 @uc2c(i8 returned zeroext %0) {
; CHECK-LABEL: uc2c:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
ret i8 %0
}
@@ -917,7 +919,6 @@ define i32 @uc2ui(i8 zeroext %0) {
define i64 @uc2ll(i8 zeroext %0) {
; CHECK-LABEL: uc2ll:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i8 %0 to i64
ret i64 %2
@@ -926,7 +927,6 @@ define i64 @uc2ll(i8 zeroext %0) {
define i64 @uc2ull(i8 zeroext %0) {
; CHECK-LABEL: uc2ull:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i8 %0 to i64
ret i64 %2
@@ -935,6 +935,7 @@ define i64 @uc2ull(i8 zeroext %0) {
define float @uc2f(i8 zeroext %x) {
; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i8 %x to float
@@ -944,6 +945,7 @@ define float @uc2f(i8 zeroext %x) {
define double @uc2d(i8 zeroext %x) {
; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i8 %x to double
@@ -976,7 +978,6 @@ define signext i8 @i1282c(i128 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i8
ret i8 %2
@@ -988,7 +989,6 @@ define signext i8 @ui1282c(i128 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i8
ret i8 %2
@@ -1020,7 +1020,6 @@ define signext i16 @i1282s(i128 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i16
ret i16 %2
@@ -1032,7 +1031,6 @@ define signext i16 @ui1282s(i128 %0) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i16
ret i16 %2
@@ -1062,7 +1060,6 @@ define zeroext i16 @ui1282us(i128 %0) {
define i32 @i1282i(i128 %0) {
; CHECK-LABEL: i1282i:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i32
ret i32 %2
@@ -1072,7 +1069,6 @@ define i32 @i1282i(i128 %0) {
define i32 @ui1282i(i128 %0) {
; CHECK-LABEL: ui1282i:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i32
ret i32 %2
@@ -1082,7 +1078,6 @@ define i32 @ui1282i(i128 %0) {
define i32 @i1282ui(i128 %0) {
; CHECK-LABEL: i1282ui:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i32
ret i32 %2
@@ -1092,7 +1087,6 @@ define i32 @i1282ui(i128 %0) {
define i32 @ui1282ui(i128 %0) {
; CHECK-LABEL: ui1282ui:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = trunc i128 %0 to i32
ret i32 %2
@@ -1216,7 +1210,7 @@ define i128 @i2ui128(i32 %0) {
define i128 @ui2i128(i32 %0) {
; CHECK-LABEL: ui2i128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i32 %0 to i128
@@ -1227,7 +1221,7 @@ define i128 @ui2i128(i32 %0) {
define i128 @ui2ui128(i32 %0) {
; CHECK-LABEL: ui2ui128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i32 %0 to i128
@@ -1238,7 +1232,6 @@ define i128 @ui2ui128(i32 %0) {
define i128 @s2i128(i16 signext %0) {
; CHECK-LABEL: s2i128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i16 %0 to i128
@@ -1249,7 +1242,6 @@ define i128 @s2i128(i16 signext %0) {
define i128 @s2ui128(i16 signext %0) {
; CHECK-LABEL: s2ui128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i16 %0 to i128
@@ -1260,7 +1252,6 @@ define i128 @s2ui128(i16 signext %0) {
define i128 @us2i128(i16 zeroext %0) {
; CHECK-LABEL: us2i128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i16 %0 to i128
@@ -1271,7 +1262,6 @@ define i128 @us2i128(i16 zeroext %0) {
define i128 @us2ui128(i16 zeroext %0) {
; CHECK-LABEL: us2ui128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i16 %0 to i128
@@ -1282,7 +1272,6 @@ define i128 @us2ui128(i16 zeroext %0) {
define i128 @c2i128(i8 signext %0) {
; CHECK-LABEL: c2i128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i8 %0 to i128
@@ -1293,7 +1282,6 @@ define i128 @c2i128(i8 signext %0) {
define i128 @char2ui128(i8 signext %0) {
; CHECK-LABEL: char2ui128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.l %s1, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%2 = sext i8 %0 to i128
@@ -1304,7 +1292,6 @@ define i128 @char2ui128(i8 signext %0) {
define i128 @uc2i128(i8 zeroext %0) {
; CHECK-LABEL: uc2i128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i8 %0 to i128
@@ -1315,7 +1302,6 @@ define i128 @uc2i128(i8 zeroext %0) {
define i128 @uc2ui128(i8 zeroext %0) {
; CHECK-LABEL: uc2ui128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = zext i8 %0 to i128
diff --git a/llvm/test/CodeGen/VE/constants.ll b/llvm/test/CodeGen/VE/constants.ll
index b7a43605ae34..baebf5ef3621 100644
--- a/llvm/test/CodeGen/VE/constants.ll
+++ b/llvm/test/CodeGen/VE/constants.ll
@@ -304,7 +304,6 @@ define float @m5f32() {
; CHECK-LABEL: m5f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s0, -1063256064
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
ret float -5.000000e+00
}
@@ -321,7 +320,6 @@ define float @p2p3f32() {
; CHECK-LABEL: p2p3f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s0, 1075000115
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
ret float 0x4002666660000000 ; 2.3
}
@@ -339,7 +337,6 @@ define float @p128p3f32() {
; CHECK-LABEL: p128p3f32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s0, 1124093133
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
ret float 0x40600999A0000000 ; 128.3
}
diff --git a/llvm/test/CodeGen/VE/ctlz.ll b/llvm/test/CodeGen/VE/ctlz.ll
index de44790014a0..5853851ac9c9 100644
--- a/llvm/test/CodeGen/VE/ctlz.ll
+++ b/llvm/test/CodeGen/VE/ctlz.ll
@@ -14,10 +14,9 @@ declare i64 @llvm.ctlz.i64(i64, i1)
define i32 @func2(i32 %p) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: ldz %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true)
ret i32 %r
diff --git a/llvm/test/CodeGen/VE/ctpop.ll b/llvm/test/CodeGen/VE/ctpop.ll
index 3d25909ab25c..8fee9104ed07 100644
--- a/llvm/test/CodeGen/VE/ctpop.ll
+++ b/llvm/test/CodeGen/VE/ctpop.ll
@@ -14,10 +14,9 @@ declare i64 @llvm.ctpop.i64(i64 %p)
define i32 @func2(i32 %p) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.ctpop.i32(i32 %p)
ret i32 %r
@@ -29,9 +28,7 @@ define i16 @func3(i16 %p) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: and %s0, %s0, (48)0
-; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.ctpop.i16(i16 %p)
ret i16 %r
@@ -43,9 +40,7 @@ define i8 @func4(i8 %p) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: and %s0, %s0, (56)0
-; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i8 @llvm.ctpop.i8(i8 %p)
ret i8 %r
diff --git a/llvm/test/CodeGen/VE/cttz.ll b/llvm/test/CodeGen/VE/cttz.ll
index 4b79a0f988e8..46bb52d29102 100644
--- a/llvm/test/CodeGen/VE/cttz.ll
+++ b/llvm/test/CodeGen/VE/cttz.ll
@@ -16,12 +16,12 @@ declare i64 @llvm.cttz.i64(i64, i1)
define i32 @func2(i32 %p) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
ret i32 %r
@@ -32,12 +32,12 @@ declare i32 @llvm.cttz.i32(i32, i1)
define i16 @func3(i16 %p) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
ret i16 %r
@@ -48,12 +48,12 @@ declare i16 @llvm.cttz.i16(i16, i1)
define i8 @func4(i8 %p) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
ret i8 %r
diff --git a/llvm/test/CodeGen/VE/div.ll b/llvm/test/CodeGen/VE/div.ll
index 8d4a0ddd2c15..ed434a9a3c7b 100644
--- a/llvm/test/CodeGen/VE/div.ll
+++ b/llvm/test/CodeGen/VE/div.ll
@@ -14,6 +14,8 @@ define i64 @divi64(i64 %a, i64 %b) {
define i32 @divi32(i32 %a, i32 %b) {
; CHECK-LABEL: divi32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 %a, %b
@@ -34,6 +36,8 @@ define i64 @divu64(i64 %a, i64 %b) {
define i32 @divu32(i32 %a, i32 %b) {
; CHECK-LABEL: divu32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 %a, %b
@@ -44,9 +48,11 @@ define i32 @divu32(i32 %a, i32 %b) {
define signext i16 @divi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: divi16:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%a32 = sext i16 %a to i32
%b32 = sext i16 %b to i32
@@ -59,7 +65,10 @@ define signext i16 @divi16(i16 signext %a, i16 signext %b) {
define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: divu16:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i16 %a, %b
ret i16 %r
@@ -69,9 +78,11 @@ define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
define signext i8 @divi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: divi8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%a32 = sext i8 %a to i32
%b32 = sext i8 %b to i32
@@ -84,7 +95,10 @@ define signext i8 @divi8(i8 signext %a, i8 signext %b) {
define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: divu8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i8 %a, %b
ret i8 %r
@@ -104,6 +118,7 @@ define i64 @divi64ri(i64 %a, i64 %b) {
define i32 @divi32ri(i32 %a, i32 %b) {
; CHECK-LABEL: divi32ri:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 %a, 3
@@ -124,6 +139,7 @@ define i64 @divu64ri(i64 %a, i64 %b) {
define i32 @divu32ri(i32 %a, i32 %b) {
; CHECK-LABEL: divu32ri:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 %a, 3
@@ -144,7 +160,8 @@ define i64 @divi64li(i64 %a, i64 %b) {
define i32 @divi32li(i32 %a, i32 %b) {
; CHECK-LABEL: divi32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: divs.w.sx %s0, 3, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: divs.w.sx %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 3, %b
ret i32 %r
@@ -164,7 +181,8 @@ define i64 @divu64li(i64 %a, i64 %b) {
define i32 @divu32li(i32 %a, i32 %b) {
; CHECK-LABEL: divu32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: divu.w %s0, 3, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: divu.w %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 3, %b
ret i32 %r
diff --git a/llvm/test/CodeGen/VE/fp_to_int.ll b/llvm/test/CodeGen/VE/fp_to_int.ll
index 9a1a7e35c119..d9b1926ea9d5 100644
--- a/llvm/test/CodeGen/VE/fp_to_int.ll
+++ b/llvm/test/CodeGen/VE/fp_to_int.ll
@@ -5,6 +5,7 @@ define signext i8 @f2c(float %a) {
; CHECK-LABEL: f2c:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptosi float %a to i8
@@ -16,6 +17,7 @@ define signext i16 @f2s(float %a) {
; CHECK-LABEL: f2s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptosi float %a to i16
@@ -50,6 +52,7 @@ define zeroext i8 @f2uc(float %a) {
; CHECK-LABEL: f2uc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptoui float %a to i8
@@ -61,6 +64,7 @@ define zeroext i16 @f2us(float %a) {
; CHECK-LABEL: f2us:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.s.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptoui float %a to i16
@@ -73,7 +77,6 @@ define i32 @f2ui(float %a) {
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptoui float %a to i32
@@ -105,6 +108,7 @@ define signext i8 @d2c(double %a) {
; CHECK-LABEL: d2c:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptosi double %a to i8
@@ -116,6 +120,7 @@ define signext i16 @d2s(double %a) {
; CHECK-LABEL: d2s:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptosi double %a to i16
@@ -149,6 +154,7 @@ define zeroext i8 @d2uc(double %a) {
; CHECK-LABEL: d2uc:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptoui double %a to i8
@@ -160,6 +166,7 @@ define zeroext i16 @d2us(double %a) {
; CHECK-LABEL: d2us:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.w.d.sx.rz %s0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptoui double %a to i16
@@ -171,7 +178,6 @@ define i32 @d2ui(double %a) {
; CHECK-LABEL: d2ui:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.l.d.rz %s0, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
entry:
%conv = fptoui double %a to i32
diff --git a/llvm/test/CodeGen/VE/int_to_fp.ll b/llvm/test/CodeGen/VE/int_to_fp.ll
index 5069a0ca0d7d..2e850142e2e9 100644
--- a/llvm/test/CodeGen/VE/int_to_fp.ll
+++ b/llvm/test/CodeGen/VE/int_to_fp.ll
@@ -4,6 +4,7 @@
define float @c2f(i8 signext %a) {
; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -15,6 +16,7 @@ entry:
define float @s2f(i16 signext %a) {
; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -26,6 +28,7 @@ entry:
define float @i2f(i32 %a) {
; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -49,6 +52,7 @@ entry:
define float @uc2f(i8 zeroext %a) {
; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -60,6 +64,7 @@ entry:
define float @us2f(i16 zeroext %a) {
; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -71,7 +76,7 @@ entry:
define float @ui2f(i32 %a) {
; CHECK-LABEL: ui2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: cvt.s.d %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
@@ -106,6 +111,7 @@ entry:
define double @c2d(i8 signext %a) {
; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -117,6 +123,7 @@ entry:
define double @s2d(i16 signext %a) {
; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -128,6 +135,7 @@ entry:
define double @i2d(i32 %a) {
; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -150,6 +158,7 @@ entry:
define double @uc2d(i8 zeroext %a) {
; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -161,6 +170,7 @@ entry:
define double @us2d(i16 zeroext %a) {
; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -172,7 +182,7 @@ entry:
define double @ui2d(i32 %a) {
; CHECK-LABEL: ui2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: cvt.d.l %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
diff --git a/llvm/test/CodeGen/VE/left_shift.ll b/llvm/test/CodeGen/VE/left_shift.ll
index d568846974dd..fa595a916e52 100644
--- a/llvm/test/CodeGen/VE/left_shift.ll
+++ b/llvm/test/CodeGen/VE/left_shift.ll
@@ -3,9 +3,11 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%3 = sext i8 %0 to i32
%4 = sext i8 %1 to i32
@@ -17,9 +19,11 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%3 = sext i16 %0 to i32
%4 = sext i16 %1 to i32
@@ -31,6 +35,8 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i32 %0, %1
@@ -50,6 +56,8 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -63,6 +71,8 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -76,6 +86,8 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i32 %0, %1
@@ -95,9 +107,10 @@ define i64 @func9(i64 %0, i64 %1) {
define signext i8 @func11(i8 signext %0) {
; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i8 %0, 5
ret i8 %2
@@ -106,9 +119,10 @@ define signext i8 @func11(i8 signext %0) {
define signext i16 @func12(i16 signext %0) {
; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i16 %0, 5
ret i16 %2
@@ -117,6 +131,7 @@ define signext i16 @func12(i16 signext %0) {
define i32 @func13(i32 %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i32 %0, 5
@@ -135,8 +150,10 @@ define i64 @func14(i64 %0) {
define zeroext i8 @func16(i8 zeroext %0) {
; CHECK-LABEL: func16:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
-; CHECK-NEXT: and %s0, %s0, (56)0
+; CHECK-NEXT: lea %s1, 224
+; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i8 %0, 5
ret i8 %2
@@ -145,8 +162,10 @@ define zeroext i8 @func16(i8 zeroext %0) {
define zeroext i16 @func17(i16 zeroext %0) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
-; CHECK-NEXT: and %s0, %s0, (48)0
+; CHECK-NEXT: lea %s1, 65504
+; CHECK-NEXT: and %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i16 %0, 5
ret i16 %2
@@ -155,6 +174,7 @@ define zeroext i16 @func17(i16 zeroext %0) {
define i32 @func18(i32 %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i32 %0, 5
diff --git a/llvm/test/CodeGen/VE/load_off.ll b/llvm/test/CodeGen/VE/load_off.ll
index cc3da7a3a1cd..2ebd616e533c 100644
--- a/llvm/test/CodeGen/VE/load_off.ll
+++ b/llvm/test/CodeGen/VE/load_off.ll
@@ -118,7 +118,7 @@ define zeroext i32 @loadi32z() {
; CHECK-NEXT: lea %s0, bufi32+8 at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, bufi32+8 at hi(, %s0)
-; CHECK-NEXT: ldl.sx %s0, (, %s0)
+; CHECK-NEXT: ldl.zx %s0, (, %s0)
; CHECK-NEXT: or %s11, 0, %s9
entry:
%0 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @bufi32, i64 0, i64 2), align 4
diff --git a/llvm/test/CodeGen/VE/max.ll b/llvm/test/CodeGen/VE/max.ll
index 67f68b02b451..2c342faa1f05 100644
--- a/llvm/test/CodeGen/VE/max.ll
+++ b/llvm/test/CodeGen/VE/max.ll
@@ -69,8 +69,6 @@ define float @max2f32(float, float) {
define float @maxuf32(float, float) {
; CHECK-LABEL: maxuf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
@@ -83,8 +81,6 @@ define float @maxuf32(float, float) {
define float @max2uf32(float, float) {
; CHECK-LABEL: max2uf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
@@ -141,6 +137,8 @@ define i64 @max2u64(i64, i64) {
define i32 @maxi32(i32, i32) {
; CHECK-LABEL: maxi32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i32 %0, %1
@@ -151,6 +149,8 @@ define i32 @maxi32(i32, i32) {
define i32 @max2i32(i32, i32) {
; CHECK-LABEL: max2i32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i32 %0, %1
@@ -161,11 +161,10 @@ define i32 @max2i32(i32, i32) {
define i32 @maxu32(i32, i32) {
; CHECK-LABEL: maxu32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s2, %s0
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
@@ -175,11 +174,10 @@ define i32 @maxu32(i32, i32) {
define i32 @max2u32(i32, i32) {
; CHECK-LABEL: max2u32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s2, %s0
+; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
diff --git a/llvm/test/CodeGen/VE/min.ll b/llvm/test/CodeGen/VE/min.ll
index 3e28f757d9e9..dd6ad8460c80 100644
--- a/llvm/test/CodeGen/VE/min.ll
+++ b/llvm/test/CodeGen/VE/min.ll
@@ -67,8 +67,6 @@ define float @min2f32(float, float) {
define float @minuf32(float, float) {
; CHECK-LABEL: minuf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
@@ -81,8 +79,6 @@ define float @minuf32(float, float) {
define float @min2uf32(float, float) {
; CHECK-LABEL: min2uf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1
-; CHECK-NEXT: # kill: def $sf0 killed $sf0 def $sx0
; CHECK-NEXT: fcmp.s %s2, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
@@ -139,6 +135,8 @@ define i64 @min2u64(i64, i64) {
define i32 @mini32(i32, i32) {
; CHECK-LABEL: mini32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i32 %0, %1
@@ -149,6 +147,8 @@ define i32 @mini32(i32, i32) {
define i32 @min2i32(i32, i32) {
; CHECK-LABEL: min2i32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i32 %0, %1
@@ -159,11 +159,10 @@ define i32 @min2i32(i32, i32) {
define i32 @minu32(i32, i32) {
; CHECK-LABEL: minu32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s2, %s0
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
@@ -173,11 +172,10 @@ define i32 @minu32(i32, i32) {
define i32 @min2u32(i32, i32) {
; CHECK-LABEL: min2u32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.le %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s2, %s0
+; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
@@ -187,10 +185,11 @@ define i32 @min2u32(i32, i32) {
define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {
; CHECK-LABEL: mini1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: and %s2, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
-; CHECK-NEXT: or %s0, 0, %s2
+; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = xor i1 %0, true
%4 = and i1 %3, %1
diff --git a/llvm/test/CodeGen/VE/multiply.ll b/llvm/test/CodeGen/VE/multiply.ll
index dabb6cf85d12..83b7a67ff453 100644
--- a/llvm/test/CodeGen/VE/multiply.ll
+++ b/llvm/test/CodeGen/VE/multiply.ll
@@ -3,9 +3,11 @@
define signext i8 @func1(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i8 %b, %a
ret i8 %r
@@ -14,9 +16,11 @@ define signext i8 @func1(i8 signext %a, i8 signext %b) {
define signext i16 @func2(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i16 %b, %a
ret i16 %r
@@ -25,6 +29,8 @@ define signext i16 @func2(i16 signext %a, i16 signext %b) {
define i32 @func3(i32 %a, i32 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i32 %b, %a
@@ -43,6 +49,8 @@ define i64 @func4(i64 %a, i64 %b) {
define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -53,6 +61,8 @@ define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -63,6 +73,8 @@ define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
define i32 @func7(i32 %a, i32 %b) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i32 %b, %a
@@ -81,9 +93,10 @@ define i64 @func8(i64 %a, i64 %b) {
define signext i8 @func9(i8 signext %a) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i8 %a, 5
ret i8 %r
@@ -92,9 +105,10 @@ define signext i8 @func9(i8 signext %a) {
define signext i16 @func10(i16 signext %a) {
; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i16 %a, 5
ret i16 %r
@@ -103,6 +117,7 @@ define signext i16 @func10(i16 signext %a) {
define i32 @func11(i32 %a) {
; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i32 %a, 5
@@ -121,6 +136,7 @@ define i64 @func12(i64 %a) {
define zeroext i8 @func13(i8 zeroext %a) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -131,6 +147,7 @@ define zeroext i8 @func13(i8 zeroext %a) {
define zeroext i16 @func14(i16 zeroext %a) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -141,6 +158,7 @@ define zeroext i16 @func14(i16 zeroext %a) {
define i32 @func15(i32 %a) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i32 %a, 5
@@ -159,6 +177,7 @@ define i64 @func16(i64 %a) {
define i32 @func17(i32 %a) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
%r = shl i32 %a, 31
diff --git a/llvm/test/CodeGen/VE/nnd.ll b/llvm/test/CodeGen/VE/nnd.ll
index aea10d4834cd..aedb85050f30 100644
--- a/llvm/test/CodeGen/VE/nnd.ll
+++ b/llvm/test/CodeGen/VE/nnd.ll
@@ -3,8 +3,11 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 %not, %b
@@ -14,8 +17,11 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) {
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s1, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 %b, %not
@@ -25,8 +31,10 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, 5, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 %not, 5
@@ -36,6 +44,7 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: and %s0, %s0, %s1
@@ -48,8 +57,11 @@ define zeroext i8 @funci8z(i8 zeroext %a) {
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 %not, %b
@@ -59,8 +71,11 @@ define signext i16 @func16s(i16 signext %a, i16 signext %b) {
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s1, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 %b, %not
@@ -70,7 +85,9 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 %not, 65535
@@ -80,8 +97,10 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, (52)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 4095, %not
@@ -91,8 +110,11 @@ define zeroext i16 @funci16z(i16 zeroext %a) {
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, %b
@@ -102,8 +124,11 @@ define signext i32 @func32s(i32 signext %a, i32 signext %b) {
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, %b
@@ -113,8 +138,10 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, (36)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, 268435455
@@ -124,8 +151,10 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: and %s0, %s0, (36)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, 268435455
diff --git a/llvm/test/CodeGen/VE/or.ll b/llvm/test/CodeGen/VE/or.ll
index 1f8c35012f81..8ddb1b5fbf80 100644
--- a/llvm/test/CodeGen/VE/or.ll
+++ b/llvm/test/CodeGen/VE/or.ll
@@ -21,7 +21,9 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, 5, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i8 %a, 5
ret i8 %res
@@ -30,8 +32,10 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: or %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i8 -5, %a
ret i8 %res
@@ -67,7 +71,9 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, %s0, (52)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i16 4095, %a
ret i16 %res
@@ -94,7 +100,9 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, %s0, (36)0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i32 %a, 268435455
ret i32 %res
@@ -103,7 +111,9 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, %s0, (36)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i32 %a, 268435455
ret i32 %res
diff --git a/llvm/test/CodeGen/VE/pic_access_static_data.ll b/llvm/test/CodeGen/VE/pic_access_static_data.ll
index e0741724172e..892aa8465d99 100644
--- a/llvm/test/CodeGen/VE/pic_access_static_data.ll
+++ b/llvm/test/CodeGen/VE/pic_access_static_data.ll
@@ -52,7 +52,7 @@ define i32 @main() {
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, dst at gotoff_hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (%s0, %s15)
-; CHECK-NEXT: stl %s1, 184(, %s11)
+; CHECK-NEXT: st %s1, 184(, %s11)
; CHECK-NEXT: lea %s0, .L.str at gotoff_lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, .L.str at gotoff_hi(, %s0)
diff --git a/llvm/test/CodeGen/VE/rem.ll b/llvm/test/CodeGen/VE/rem.ll
index 9fa558f5ca3c..52ac3c3a3c9e 100644
--- a/llvm/test/CodeGen/VE/rem.ll
+++ b/llvm/test/CodeGen/VE/rem.ll
@@ -16,6 +16,8 @@ define i64 @remi64(i64 %a, i64 %b) {
define i32 @remi32(i32 %a, i32 %b) {
; CHECK-LABEL: remi32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -40,6 +42,8 @@ define i64 @remu64(i64 %a, i64 %b) {
define i32 @remu32(i32 %a, i32 %b) {
; CHECK-LABEL: remu32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -52,11 +56,13 @@ define i32 @remu32(i32 %a, i32 %b) {
define signext i16 @remi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: remi16:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%a32 = sext i16 %a to i32
%b32 = sext i16 %b to i32
@@ -69,9 +75,12 @@ define signext i16 @remi16(i16 signext %a, i16 signext %b) {
define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: remu16:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = urem i16 %a, %b
ret i16 %r
@@ -81,11 +90,13 @@ define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
define signext i8 @remi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: remi8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%a32 = sext i8 %a to i32
%b32 = sext i8 %b to i32
@@ -98,9 +109,12 @@ define signext i8 @remi8(i8 signext %a, i8 signext %b) {
define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: remu8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%r = urem i8 %a, %b
ret i8 %r
@@ -122,6 +136,7 @@ define i64 @remi64ri(i64 %a, i64 %b) {
define i32 @remi32ri(i32 %a, i32 %b) {
; CHECK-LABEL: remi32ri:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -146,6 +161,7 @@ define i64 @remu64ri(i64 %a, i64 %b) {
define i32 @remu32ri(i32 %a, i32 %b) {
; CHECK-LABEL: remu32ri:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -170,8 +186,9 @@ define i64 @remi64li(i64 %a, i64 %b) {
define i32 @remi32li(i32 %a, i32 %b) {
; CHECK-LABEL: remi32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: divs.w.sx %s0, 3, %s1
-; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: divs.w.sx %s1, 3, %s0
+; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = srem i32 3, %b
@@ -194,8 +211,9 @@ define i64 @remu64li(i64 %a, i64 %b) {
define i32 @remu32li(i32 %a, i32 %b) {
; CHECK-LABEL: remu32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: divu.w %s0, 3, %s1
-; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
+; CHECK-NEXT: divu.w %s1, 3, %s0
+; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = urem i32 3, %b
diff --git a/llvm/test/CodeGen/VE/right_shift.ll b/llvm/test/CodeGen/VE/right_shift.ll
index faad722a3053..87ac6df7e62e 100644
--- a/llvm/test/CodeGen/VE/right_shift.ll
+++ b/llvm/test/CodeGen/VE/right_shift.ll
@@ -3,7 +3,10 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = sext i8 %0 to i32
%4 = sext i8 %1 to i32
@@ -15,7 +18,10 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = sext i16 %0 to i32
%4 = sext i16 %1 to i32
@@ -27,6 +33,8 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = ashr i32 %0, %1
@@ -46,10 +54,11 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = zext i8 %0 to i32
%4 = zext i8 %1 to i32
@@ -61,10 +70,11 @@ define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = zext i16 %0 to i32
%4 = zext i16 %1 to i32
@@ -76,10 +86,10 @@ define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
define i32 @func9(i32 %0, i32 %1) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = lshr i32 %0, %1
ret i32 %3
@@ -98,7 +108,9 @@ define i64 @func10(i64 %0, i64 %1) {
define signext i8 @func12(i8 signext %0) {
; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = ashr i8 %0, 5
ret i8 %2
@@ -107,7 +119,9 @@ define signext i8 @func12(i8 signext %0) {
define signext i16 @func13(i16 signext %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = ashr i16 %0, 5
ret i16 %2
@@ -116,6 +130,7 @@ define signext i16 @func13(i16 signext %0) {
define i32 @func14(i32 %0) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
%2 = ashr i32 %0, 5
@@ -134,10 +149,10 @@ define i64 @func15(i64 %0) {
define zeroext i8 @func17(i8 zeroext %0) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = lshr i8 %0, 5
ret i8 %2
@@ -146,10 +161,10 @@ define zeroext i8 @func17(i8 zeroext %0) {
define zeroext i16 @func18(i16 zeroext %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = lshr i16 %0, 5
ret i16 %2
@@ -158,10 +173,9 @@ define zeroext i16 @func18(i16 zeroext %0) {
define i32 @func19(i32 %0) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%2 = lshr i32 %0, 5
ret i32 %2
diff --git a/llvm/test/CodeGen/VE/rotl.ll b/llvm/test/CodeGen/VE/rotl.ll
index e7c498f1d34d..cc5e004478ab 100644
--- a/llvm/test/CodeGen/VE/rotl.ll
+++ b/llvm/test/CodeGen/VE/rotl.ll
@@ -3,6 +3,7 @@
define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: sll %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
@@ -21,7 +22,8 @@ define i64 @func1(i64 %a, i32 %b) {
define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s2, %s0, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
diff --git a/llvm/test/CodeGen/VE/rotr.ll b/llvm/test/CodeGen/VE/rotr.ll
index 40734a3d5178..93dcbbc7e0a8 100644
--- a/llvm/test/CodeGen/VE/rotr.ll
+++ b/llvm/test/CodeGen/VE/rotr.ll
@@ -3,6 +3,7 @@
define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: srl %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
@@ -21,7 +22,8 @@ define i64 @func1(i64 %a, i32 %b) {
define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s2, %s0, (32)0
; CHECK-NEXT: srl %s2, %s2, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1
diff --git a/llvm/test/CodeGen/VE/select.ll b/llvm/test/CodeGen/VE/select.ll
index 6efe073381d5..81234d3d955c 100644
--- a/llvm/test/CodeGen/VE/select.ll
+++ b/llvm/test/CodeGen/VE/select.ll
@@ -3,6 +3,7 @@
define double @selectf64(i1 zeroext, double, double) {
; CHECK-LABEL: selectf64:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
@@ -13,8 +14,7 @@ define double @selectf64(i1 zeroext, double, double) {
define float @selectf32(i1 zeroext, float, float) {
; CHECK-LABEL: selectf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
-; CHECK-NEXT: # kill: def $sf1 killed $sf1 def $sx1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
@@ -25,6 +25,7 @@ define float @selectf32(i1 zeroext, float, float) {
define i64 @selecti64(i1 zeroext, i64, i64) {
; CHECK-LABEL: selecti64:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
@@ -35,10 +36,10 @@ define i64 @selecti64(i1 zeroext, i64, i64) {
define i32 @selecti32(i1 zeroext, i32, i32) {
; CHECK-LABEL: selecti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
-; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
-; CHECK-NEXT: or %s0, 0, %s2
+; CHECK-NEXT: adds.w.sx %s3, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
+; CHECK-NEXT: cmov.w.ne %s0, %s1, %s3
; CHECK-NEXT: or %s11, 0, %s9
%4 = select i1 %0, i32 %1, i32 %2
ret i32 %4
@@ -47,10 +48,11 @@ define i32 @selecti32(i1 zeroext, i32, i32) {
define zeroext i1 @selecti1(i1 zeroext, i1 zeroext, i1 zeroext) {
; CHECK-LABEL: selecti1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: # kill: def $sw1 killed $sw1 def $sx1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
-; CHECK-NEXT: or %s0, 0, %s2
+; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%4 = select i1 %0, i1 %1, i1 %2
ret i1 %4
diff --git a/llvm/test/CodeGen/VE/selectccf32.ll b/llvm/test/CodeGen/VE/selectccf32.ll
index 748a3e927557..2832be6bc12a 100644
--- a/llvm/test/CodeGen/VE/selectccf32.ll
+++ b/llvm/test/CodeGen/VE/selectccf32.ll
@@ -23,8 +23,6 @@ define float @selectccat(float, float, float, float) {
define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -37,8 +35,6 @@ define float @selectccoeq(float, float, float, float) {
define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -51,8 +47,6 @@ define float @selectccone(float, float, float, float) {
define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -65,8 +59,6 @@ define float @selectccogt(float, float, float, float) {
define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -79,8 +71,6 @@ define float @selectccoge(float, float, float, float) {
define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -93,8 +83,6 @@ define float @selectccolt(float, float, float, float) {
define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -107,8 +95,6 @@ define float @selectccole(float, float, float, float) {
define float @selectccord(float, float, float, float) {
; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -121,8 +107,6 @@ define float @selectccord(float, float, float, float) {
define float @selectccuno(float, float, float, float) {
; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -135,8 +119,6 @@ define float @selectccuno(float, float, float, float) {
define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -149,8 +131,6 @@ define float @selectccueq(float, float, float, float) {
define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -163,8 +143,6 @@ define float @selectccune(float, float, float, float) {
define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -177,8 +155,6 @@ define float @selectccugt(float, float, float, float) {
define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -191,8 +167,6 @@ define float @selectccuge(float, float, float, float) {
define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -205,8 +179,6 @@ define float @selectccult(float, float, float, float) {
define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/selectccf32c.ll b/llvm/test/CodeGen/VE/selectccf32c.ll
index 78a9aaf96729..54a9da4c8e46 100644
--- a/llvm/test/CodeGen/VE/selectccf32c.ll
+++ b/llvm/test/CodeGen/VE/selectccf32c.ll
@@ -3,12 +3,10 @@
define float @selectccsgti8(i8, i8, float, float) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
-; CHECK-NEXT: sla.w.sx %s1, %s1, 24
-; CHECK-NEXT: sra.w.sx %s1, %s1, 24
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s1, %s1, 56
+; CHECK-NEXT: sra.l %s1, %s1, 56
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -21,12 +19,10 @@ define float @selectccsgti8(i8, i8, float, float) {
define float @selectccsgti16(i16, i16, float, float) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
-; CHECK-NEXT: sla.w.sx %s1, %s1, 16
-; CHECK-NEXT: sra.w.sx %s1, %s1, 16
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s1, %s1, 48
+; CHECK-NEXT: sra.l %s1, %s1, 48
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -39,8 +35,8 @@ define float @selectccsgti16(i16, i16, float, float) {
define float @selectccsgti32(i32, i32, float, float) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -53,8 +49,6 @@ define float @selectccsgti32(i32, i32, float, float) {
define float @selectccsgti64(i64, i64, float, float) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: cmps.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -67,8 +61,6 @@ define float @selectccsgti64(i64, i64, float, float) {
define float @selectccsgti128(i128, i128, float, float) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf5 killed $sf5 def $sx5
-; CHECK-NEXT: # kill: def $sf4 killed $sf4 def $sx4
; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, %s6
@@ -89,8 +81,6 @@ define float @selectccsgti128(i128, i128, float, float) {
define float @selectccogtf32(float, float, float, float) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -103,8 +93,6 @@ define float @selectccogtf32(float, float, float, float) {
define float @selectccogtf64(double, double, float, float) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/selectccf32i.ll b/llvm/test/CodeGen/VE/selectccf32i.ll
index e8285c818c54..5e2698b4feb1 100644
--- a/llvm/test/CodeGen/VE/selectccf32i.ll
+++ b/llvm/test/CodeGen/VE/selectccf32i.ll
@@ -23,8 +23,6 @@ define float @selectccat(float, float, float, float) {
define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
@@ -38,8 +36,6 @@ define float @selectccoeq(float, float, float, float) {
define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
@@ -53,8 +49,6 @@ define float @selectccone(float, float, float, float) {
define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
@@ -68,8 +62,6 @@ define float @selectccogt(float, float, float, float) {
define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
@@ -83,8 +75,6 @@ define float @selectccoge(float, float, float, float) {
define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
@@ -98,8 +88,6 @@ define float @selectccolt(float, float, float, float) {
define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
@@ -113,8 +101,6 @@ define float @selectccole(float, float, float, float) {
define float @selectccord(float, float, float, float) {
; CHECK-LABEL: selectccord:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: cmov.s.num %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -127,8 +113,6 @@ define float @selectccord(float, float, float, float) {
define float @selectccuno(float, float, float, float) {
; CHECK-LABEL: selectccuno:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: fcmp.s %s0, %s0, %s0
; CHECK-NEXT: cmov.s.nan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -141,8 +125,6 @@ define float @selectccuno(float, float, float, float) {
define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
@@ -156,8 +138,6 @@ define float @selectccueq(float, float, float, float) {
define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
@@ -171,8 +151,6 @@ define float @selectccune(float, float, float, float) {
define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
@@ -186,8 +164,6 @@ define float @selectccugt(float, float, float, float) {
define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
@@ -201,8 +177,6 @@ define float @selectccuge(float, float, float, float) {
define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
@@ -216,8 +190,6 @@ define float @selectccult(float, float, float, float) {
define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sf3 killed $sf3 def $sx3
-; CHECK-NEXT: # kill: def $sf2 killed $sf2 def $sx2
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
diff --git a/llvm/test/CodeGen/VE/selectccf64c.ll b/llvm/test/CodeGen/VE/selectccf64c.ll
index 4481d1d6197f..24b61ece8d54 100644
--- a/llvm/test/CodeGen/VE/selectccf64c.ll
+++ b/llvm/test/CodeGen/VE/selectccf64c.ll
@@ -3,10 +3,10 @@
define double @selectccsgti8(i8, i8, double, double) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s1, %s1, 24
-; CHECK-NEXT: sra.w.sx %s1, %s1, 24
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s1, %s1, 56
+; CHECK-NEXT: sra.l %s1, %s1, 56
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -19,10 +19,10 @@ define double @selectccsgti8(i8, i8, double, double) {
define double @selectccsgti16(i16, i16, double, double) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s1, %s1, 16
-; CHECK-NEXT: sra.w.sx %s1, %s1, 16
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s1, %s1, 48
+; CHECK-NEXT: sra.l %s1, %s1, 48
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -35,6 +35,8 @@ define double @selectccsgti16(i16, i16, double, double) {
define double @selectccsgti32(i32, i32, double, double) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/selectcci32.ll b/llvm/test/CodeGen/VE/selectcci32.ll
index eea115c8b936..af1861487b89 100644
--- a/llvm/test/CodeGen/VE/selectcci32.ll
+++ b/llvm/test/CodeGen/VE/selectcci32.ll
@@ -3,11 +3,12 @@
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.eq %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -17,11 +18,12 @@ define i32 @selectcceq(i32, i32, i32, i32) {
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.ne %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ne i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -31,11 +33,12 @@ define i32 @selectccne(i32, i32, i32, i32) {
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -45,11 +48,12 @@ define i32 @selectccsgt(i32, i32, i32, i32) {
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -59,11 +63,12 @@ define i32 @selectccsge(i32, i32, i32, i32) {
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp slt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -73,11 +78,12 @@ define i32 @selectccslt(i32, i32, i32, i32) {
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sle i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -87,11 +93,12 @@ define i32 @selectccsle(i32, i32, i32, i32) {
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -101,11 +108,12 @@ define i32 @selectccugt(i32, i32, i32, i32) {
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -115,11 +123,12 @@ define i32 @selectccuge(i32, i32, i32, i32) {
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -129,11 +138,12 @@ define i32 @selectccult(i32, i32, i32, i32) {
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -143,11 +153,12 @@ define i32 @selectccule(i32, i32, i32, i32) {
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -157,11 +168,12 @@ define i32 @selectccugt2(i32, i32, i32, i32) {
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -171,11 +183,12 @@ define i32 @selectccuge2(i32, i32, i32, i32) {
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -185,11 +198,12 @@ define i32 @selectccult2(i32, i32, i32, i32) {
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
diff --git a/llvm/test/CodeGen/VE/selectcci32c.ll b/llvm/test/CodeGen/VE/selectcci32c.ll
index 474e9e0dcd4d..e4017c46c579 100644
--- a/llvm/test/CodeGen/VE/selectcci32c.ll
+++ b/llvm/test/CodeGen/VE/selectcci32c.ll
@@ -3,15 +3,14 @@
define i32 @selectccsgti8(i8, i8, i32, i32) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: sla.w.sx %s1, %s1, 24
-; CHECK-NEXT: sra.w.sx %s1, %s1, 24
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: sll %s1, %s1, 56
+; CHECK-NEXT: sra.l %s1, %s1, 56
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s4, %s0, 56
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -21,15 +20,14 @@ define i32 @selectccsgti8(i8, i8, i32, i32) {
define i32 @selectccsgti16(i16, i16, i32, i32) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: sla.w.sx %s1, %s1, 16
-; CHECK-NEXT: sra.w.sx %s1, %s1, 16
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: sll %s1, %s1, 48
+; CHECK-NEXT: sra.l %s1, %s1, 48
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s4, %s0, 48
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -39,11 +37,12 @@ define i32 @selectccsgti16(i16, i16, i32, i32) {
define i32 @selectccsgti32(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -53,11 +52,11 @@ define i32 @selectccsgti32(i32, i32, i32, i32) {
define i32 @selectccsgti64(i64, i64, i32, i32) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
+; CHECK-NEXT: adds.w.sx %s4, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s3, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: cmov.l.gt %s2, %s4, %s0
+; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -67,19 +66,19 @@ define i32 @selectccsgti64(i64, i64, i32, i32) {
define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw5 killed $sw5 def $sx5
-; CHECK-NEXT: # kill: def $sw4 killed $sw4 def $sx4
-; CHECK-NEXT: or %s6, 0, (0)1
+; CHECK-NEXT: adds.w.sx %s6, %s4, (0)1
+; CHECK-NEXT: adds.w.sx %s4, %s5, (0)1
+; CHECK-NEXT: or %s5, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s3
-; CHECK-NEXT: or %s3, 0, %s6
+; CHECK-NEXT: or %s3, 0, %s5
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1
+; CHECK-NEXT: cmov.l.gt %s5, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s5, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0
-; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
-; CHECK-NEXT: or %s0, 0, %s5
+; CHECK-NEXT: cmov.w.ne %s4, %s6, %s0
+; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -89,11 +88,11 @@ define i32 @selectccsgti128(i128, i128, i32, i32) {
define i32 @selectccogtf32(float, float, i32, i32) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
+; CHECK-NEXT: adds.w.sx %s4, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s3, (0)1
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
-; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: cmov.s.gt %s2, %s4, %s0
+; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -103,11 +102,11 @@ define i32 @selectccogtf32(float, float, i32, i32) {
define i32 @selectccogtf64(double, double, i32, i32) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
+; CHECK-NEXT: adds.w.sx %s4, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s3, (0)1
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
-; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: cmov.d.gt %s2, %s4, %s0
+; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, i32 %2, i32 %3
diff --git a/llvm/test/CodeGen/VE/selectcci32i.ll b/llvm/test/CodeGen/VE/selectcci32i.ll
index 0e17f83ad178..a4cccd0ebf93 100644
--- a/llvm/test/CodeGen/VE/selectcci32i.ll
+++ b/llvm/test/CodeGen/VE/selectcci32i.ll
@@ -3,12 +3,12 @@
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.eq %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp eq i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -18,12 +18,12 @@ define i32 @selectcceq(i32, i32, i32, i32) {
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.ne %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ne i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -33,12 +33,12 @@ define i32 @selectccne(i32, i32, i32, i32) {
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -48,12 +48,12 @@ define i32 @selectccsgt(i32, i32, i32, i32) {
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 11, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -63,12 +63,12 @@ define i32 @selectccsge(i32, i32, i32, i32) {
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp slt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -78,12 +78,12 @@ define i32 @selectccslt(i32, i32, i32, i32) {
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 13, (0)1
+; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sle i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -93,12 +93,12 @@ define i32 @selectccsle(i32, i32, i32, i32) {
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -108,12 +108,12 @@ define i32 @selectccugt(i32, i32, i32, i32) {
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 11, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -123,12 +123,12 @@ define i32 @selectccuge(i32, i32, i32, i32) {
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -138,12 +138,12 @@ define i32 @selectccult(i32, i32, i32, i32) {
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 13, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -153,12 +153,12 @@ define i32 @selectccule(i32, i32, i32, i32) {
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -168,12 +168,12 @@ define i32 @selectccugt2(i32, i32, i32, i32) {
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 11, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -183,12 +183,12 @@ define i32 @selectccuge2(i32, i32, i32, i32) {
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 12, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -198,12 +198,12 @@ define i32 @selectccult2(i32, i32, i32, i32) {
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: # kill: def $sw3 killed $sw3 def $sx3
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 def $sx2
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
-; CHECK-NEXT: or %s0, 0, %s3
+; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
+; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
+; CHECK-NEXT: or %s3, 13, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s1, %s3
+; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
diff --git a/llvm/test/CodeGen/VE/selectcci64c.ll b/llvm/test/CodeGen/VE/selectcci64c.ll
index 7bb7d7fee1c3..276f23d9a5ff 100644
--- a/llvm/test/CodeGen/VE/selectcci64c.ll
+++ b/llvm/test/CodeGen/VE/selectcci64c.ll
@@ -3,10 +3,10 @@
define i64 @selectccsgti8(i8, i8, i64, i64) {
; CHECK-LABEL: selectccsgti8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s1, %s1, 24
-; CHECK-NEXT: sra.w.sx %s1, %s1, 24
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s1, %s1, 56
+; CHECK-NEXT: sra.l %s1, %s1, 56
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -19,10 +19,10 @@ define i64 @selectccsgti8(i8, i8, i64, i64) {
define i64 @selectccsgti16(i16, i16, i64, i64) {
; CHECK-LABEL: selectccsgti16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: sla.w.sx %s1, %s1, 16
-; CHECK-NEXT: sra.w.sx %s1, %s1, 16
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s1, %s1, 48
+; CHECK-NEXT: sra.l %s1, %s1, 48
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
@@ -35,6 +35,8 @@ define i64 @selectccsgti16(i16, i16, i64, i64) {
define i64 @selectccsgti32(i32, i32, i64, i64) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/setccf32.ll b/llvm/test/CodeGen/VE/setccf32.ll
index 6ced8ce53b9c..f2e9062fcf62 100644
--- a/llvm/test/CodeGen/VE/setccf32.ll
+++ b/llvm/test/CodeGen/VE/setccf32.ll
@@ -21,10 +21,10 @@ define zeroext i1 @setccat(float, float) {
define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq float %0, %1
ret i1 %3
@@ -33,10 +33,10 @@ define zeroext i1 @setccoeq(float, float) {
define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one float %0, %1
ret i1 %3
@@ -45,10 +45,10 @@ define zeroext i1 @setccone(float, float) {
define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt float %0, %1
ret i1 %3
@@ -57,10 +57,10 @@ define zeroext i1 @setccogt(float, float) {
define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge float %0, %1
ret i1 %3
@@ -69,10 +69,10 @@ define zeroext i1 @setccoge(float, float) {
define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt float %0, %1
ret i1 %3
@@ -81,10 +81,10 @@ define zeroext i1 @setccolt(float, float) {
define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole float %0, %1
ret i1 %3
@@ -93,10 +93,10 @@ define zeroext i1 @setccole(float, float) {
define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.num %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord float %0, %1
ret i1 %3
@@ -105,10 +105,10 @@ define zeroext i1 @setccord(float, float) {
define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.nan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno float %0, %1
ret i1 %3
@@ -117,10 +117,10 @@ define zeroext i1 @setccuno(float, float) {
define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.eqnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq float %0, %1
ret i1 %3
@@ -129,10 +129,10 @@ define zeroext i1 @setccueq(float, float) {
define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.nenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une float %0, %1
ret i1 %3
@@ -141,10 +141,10 @@ define zeroext i1 @setccune(float, float) {
define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.gtnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt float %0, %1
ret i1 %3
@@ -153,10 +153,10 @@ define zeroext i1 @setccugt(float, float) {
define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.genan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge float %0, %1
ret i1 %3
@@ -165,10 +165,10 @@ define zeroext i1 @setccuge(float, float) {
define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.ltnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult float %0, %1
ret i1 %3
@@ -177,10 +177,10 @@ define zeroext i1 @setccult(float, float) {
define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.lenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule float %0, %1
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setccf32i.ll b/llvm/test/CodeGen/VE/setccf32i.ll
index 8f79219359f3..3f90a103fec5 100644
--- a/llvm/test/CodeGen/VE/setccf32i.ll
+++ b/llvm/test/CodeGen/VE/setccf32i.ll
@@ -22,10 +22,10 @@ define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq float %0, 0.0
ret i1 %3
@@ -35,10 +35,10 @@ define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one float %0, 0.0
ret i1 %3
@@ -48,10 +48,10 @@ define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt float %0, 0.0
ret i1 %3
@@ -61,10 +61,10 @@ define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge float %0, 0.0
ret i1 %3
@@ -74,10 +74,10 @@ define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt float %0, 0.0
ret i1 %3
@@ -87,10 +87,10 @@ define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole float %0, 0.0
ret i1 %3
@@ -99,10 +99,10 @@ define zeroext i1 @setccole(float, float) {
define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s0
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.num %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s0
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.num %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord float %0, 0.0
ret i1 %3
@@ -111,10 +111,10 @@ define zeroext i1 @setccord(float, float) {
define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.s %s1, %s0, %s0
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.nan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s0
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.nan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno float %0, 0.0
ret i1 %3
@@ -124,10 +124,10 @@ define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.eqnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.eqnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq float %0, 0.0
ret i1 %3
@@ -137,10 +137,10 @@ define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.nenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.nenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une float %0, 0.0
ret i1 %3
@@ -150,10 +150,10 @@ define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.gtnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.gtnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt float %0, 0.0
ret i1 %3
@@ -163,10 +163,10 @@ define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.genan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.genan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge float %0, 0.0
ret i1 %3
@@ -176,10 +176,10 @@ define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.ltnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.ltnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult float %0, 0.0
ret i1 %3
@@ -189,10 +189,10 @@ define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.s.lenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.s %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.s.lenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule float %0, 0.0
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setccf64.ll b/llvm/test/CodeGen/VE/setccf64.ll
index dca40e8231fa..98c0e6c56bf4 100644
--- a/llvm/test/CodeGen/VE/setccf64.ll
+++ b/llvm/test/CodeGen/VE/setccf64.ll
@@ -21,10 +21,10 @@ define zeroext i1 @setccat(double, double) {
define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq double %0, %1
ret i1 %3
@@ -33,10 +33,10 @@ define zeroext i1 @setccoeq(double, double) {
define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one double %0, %1
ret i1 %3
@@ -45,10 +45,10 @@ define zeroext i1 @setccone(double, double) {
define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt double %0, %1
ret i1 %3
@@ -57,10 +57,10 @@ define zeroext i1 @setccogt(double, double) {
define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge double %0, %1
ret i1 %3
@@ -69,10 +69,10 @@ define zeroext i1 @setccoge(double, double) {
define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt double %0, %1
ret i1 %3
@@ -81,10 +81,10 @@ define zeroext i1 @setccolt(double, double) {
define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole double %0, %1
ret i1 %3
@@ -93,10 +93,10 @@ define zeroext i1 @setccole(double, double) {
define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.num %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord double %0, %1
ret i1 %3
@@ -105,10 +105,10 @@ define zeroext i1 @setccord(double, double) {
define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.nan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno double %0, %1
ret i1 %3
@@ -117,10 +117,10 @@ define zeroext i1 @setccuno(double, double) {
define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.eqnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq double %0, %1
ret i1 %3
@@ -129,10 +129,10 @@ define zeroext i1 @setccueq(double, double) {
define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.nenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une double %0, %1
ret i1 %3
@@ -141,10 +141,10 @@ define zeroext i1 @setccune(double, double) {
define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.gtnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt double %0, %1
ret i1 %3
@@ -153,10 +153,10 @@ define zeroext i1 @setccugt(double, double) {
define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.genan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge double %0, %1
ret i1 %3
@@ -165,10 +165,10 @@ define zeroext i1 @setccuge(double, double) {
define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.ltnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult double %0, %1
ret i1 %3
@@ -177,10 +177,10 @@ define zeroext i1 @setccult(double, double) {
define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.lenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule double %0, %1
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setccf64i.ll b/llvm/test/CodeGen/VE/setccf64i.ll
index 59af1b4103f6..f3a8d2f35f6f 100644
--- a/llvm/test/CodeGen/VE/setccf64i.ll
+++ b/llvm/test/CodeGen/VE/setccf64i.ll
@@ -22,10 +22,10 @@ define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq double %0, 0.0
ret i1 %3
@@ -35,10 +35,10 @@ define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one double %0, 0.0
ret i1 %3
@@ -48,10 +48,10 @@ define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt double %0, 0.0
ret i1 %3
@@ -61,10 +61,10 @@ define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge double %0, 0.0
ret i1 %3
@@ -74,10 +74,10 @@ define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt double %0, 0.0
ret i1 %3
@@ -87,10 +87,10 @@ define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole double %0, 0.0
ret i1 %3
@@ -99,10 +99,10 @@ define zeroext i1 @setccole(double, double) {
define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s0
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.num %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s0
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.num %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord double %0, 0.0
ret i1 %3
@@ -111,10 +111,10 @@ define zeroext i1 @setccord(double, double) {
define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: fcmp.d %s1, %s0, %s0
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.nan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s0
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.nan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno double %0, 0.0
ret i1 %3
@@ -124,10 +124,10 @@ define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.eqnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.eqnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq double %0, 0.0
ret i1 %3
@@ -137,10 +137,10 @@ define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.nenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.nenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une double %0, 0.0
ret i1 %3
@@ -150,10 +150,10 @@ define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.gtnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.gtnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt double %0, 0.0
ret i1 %3
@@ -163,10 +163,10 @@ define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.genan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.genan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge double %0, 0.0
ret i1 %3
@@ -176,10 +176,10 @@ define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.ltnan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.ltnan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult double %0, 0.0
ret i1 %3
@@ -189,10 +189,10 @@ define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.d.lenan %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: fcmp.d %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.d.lenan %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule double %0, 0.0
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setcci32.ll b/llvm/test/CodeGen/VE/setcci32.ll
index 7e92a2c7f5ed..15bf130fec8b 100644
--- a/llvm/test/CodeGen/VE/setcci32.ll
+++ b/llvm/test/CodeGen/VE/setcci32.ll
@@ -3,10 +3,12 @@
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i32 %0, %1
ret i1 %3
@@ -15,10 +17,12 @@ define zeroext i1 @setcceq(i32, i32) {
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i32 %0, %1
ret i1 %3
@@ -27,10 +31,12 @@ define zeroext i1 @setccne(i32, i32) {
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i32 %0, %1
ret i1 %3
@@ -39,10 +45,12 @@ define zeroext i1 @setccugt(i32, i32) {
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i32 %0, %1
ret i1 %3
@@ -51,10 +59,12 @@ define zeroext i1 @setccuge(i32, i32) {
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i32 %0, %1
ret i1 %3
@@ -63,10 +73,12 @@ define zeroext i1 @setccult(i32, i32) {
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i32 %0, %1
ret i1 %3
@@ -75,10 +87,12 @@ define zeroext i1 @setccule(i32, i32) {
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i32 %0, %1
ret i1 %3
@@ -87,10 +101,12 @@ define zeroext i1 @setccsgt(i32, i32) {
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i32 %0, %1
ret i1 %3
@@ -99,10 +115,12 @@ define zeroext i1 @setccsge(i32, i32) {
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i32 %0, %1
ret i1 %3
@@ -111,10 +129,12 @@ define zeroext i1 @setccslt(i32, i32) {
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i32 %0, %1
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setcci32i.ll b/llvm/test/CodeGen/VE/setcci32i.ll
index c0d1fb0a67e4..ac226190ae44 100644
--- a/llvm/test/CodeGen/VE/setcci32i.ll
+++ b/llvm/test/CodeGen/VE/setcci32i.ll
@@ -3,11 +3,12 @@
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i32 %0, 12
ret i1 %3
@@ -16,11 +17,12 @@ define zeroext i1 @setcceq(i32, i32) {
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i32 %0, 12
ret i1 %3
@@ -29,11 +31,12 @@ define zeroext i1 @setccne(i32, i32) {
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i32 %0, 12
ret i1 %3
@@ -42,11 +45,12 @@ define zeroext i1 @setccugt(i32, i32) {
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i32 %0, 12
ret i1 %3
@@ -55,11 +59,12 @@ define zeroext i1 @setccuge(i32, i32) {
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i32 %0, 12
ret i1 %3
@@ -68,11 +73,12 @@ define zeroext i1 @setccult(i32, i32) {
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i32 %0, 12
ret i1 %3
@@ -81,11 +87,12 @@ define zeroext i1 @setccule(i32, i32) {
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i32 %0, 12
ret i1 %3
@@ -94,11 +101,12 @@ define zeroext i1 @setccsgt(i32, i32) {
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i32 %0, 12
ret i1 %3
@@ -107,11 +115,12 @@ define zeroext i1 @setccsge(i32, i32) {
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i32 %0, 12
ret i1 %3
@@ -120,11 +129,12 @@ define zeroext i1 @setccslt(i32, i32) {
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i32 %0, 12
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setcci64.ll b/llvm/test/CodeGen/VE/setcci64.ll
index 8b86601594da..5cae80a60f06 100644
--- a/llvm/test/CodeGen/VE/setcci64.ll
+++ b/llvm/test/CodeGen/VE/setcci64.ll
@@ -3,10 +3,10 @@
define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i64 %0, %1
ret i1 %3
@@ -15,10 +15,10 @@ define zeroext i1 @setcceq(i64, i64) {
define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i64 %0, %1
ret i1 %3
@@ -27,10 +27,10 @@ define zeroext i1 @setccne(i64, i64) {
define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i64 %0, %1
ret i1 %3
@@ -39,10 +39,10 @@ define zeroext i1 @setccugt(i64, i64) {
define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i64 %0, %1
ret i1 %3
@@ -51,10 +51,10 @@ define zeroext i1 @setccuge(i64, i64) {
define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i64 %0, %1
ret i1 %3
@@ -63,10 +63,10 @@ define zeroext i1 @setccult(i64, i64) {
define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i64 %0, %1
ret i1 %3
@@ -75,10 +75,10 @@ define zeroext i1 @setccule(i64, i64) {
define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i64 %0, %1
ret i1 %3
@@ -87,10 +87,10 @@ define zeroext i1 @setccsgt(i64, i64) {
define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.ge %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.ge %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i64 %0, %1
ret i1 %3
@@ -99,10 +99,10 @@ define zeroext i1 @setccsge(i64, i64) {
define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i64 %0, %1
ret i1 %3
@@ -111,10 +111,10 @@ define zeroext i1 @setccslt(i64, i64) {
define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.le %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.le %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i64 %0, %1
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/setcci64i.ll b/llvm/test/CodeGen/VE/setcci64i.ll
index aecbe40b0a34..c73db4c72276 100644
--- a/llvm/test/CodeGen/VE/setcci64i.ll
+++ b/llvm/test/CodeGen/VE/setcci64i.ll
@@ -4,10 +4,10 @@ define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i64 %0, 12
ret i1 %3
@@ -17,10 +17,10 @@ define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.ne %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i64 %0, 12
ret i1 %3
@@ -30,10 +30,10 @@ define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i64 %0, 12
ret i1 %3
@@ -43,10 +43,10 @@ define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i64 %0, 12
ret i1 %3
@@ -56,10 +56,10 @@ define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i64 %0, 12
ret i1 %3
@@ -69,10 +69,10 @@ define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i64 %0, 12
ret i1 %3
@@ -82,10 +82,10 @@ define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i64 %0, 12
ret i1 %3
@@ -95,10 +95,10 @@ define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i64 %0, 12
ret i1 %3
@@ -108,10 +108,10 @@ define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i64 %0, 12
ret i1 %3
@@ -121,10 +121,10 @@ define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmps.l %s1, %s0, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
-; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
+; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s1, (63)0, %s0
+; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i64 %0, 12
ret i1 %3
diff --git a/llvm/test/CodeGen/VE/sext_zext_load.ll b/llvm/test/CodeGen/VE/sext_zext_load.ll
index b9fc6bc4daf7..600a02a5b130 100644
--- a/llvm/test/CodeGen/VE/sext_zext_load.ll
+++ b/llvm/test/CodeGen/VE/sext_zext_load.ll
@@ -267,8 +267,8 @@ define signext i8 @func37() {
; CHECK-LABEL: func37:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT: sla.w.sx %s0, %s0, 31
-; CHECK-NEXT: sra.w.sx %s0, %s0, 31
+; CHECK-NEXT: sll %s0, %s0, 63
+; CHECK-NEXT: sra.l %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
@@ -280,8 +280,8 @@ define signext i16 @func38() {
; CHECK-LABEL: func38:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT: sla.w.sx %s0, %s0, 31
-; CHECK-NEXT: sra.w.sx %s0, %s0, 31
+; CHECK-NEXT: sll %s0, %s0, 63
+; CHECK-NEXT: sra.l %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
@@ -293,8 +293,8 @@ define signext i32 @func39() {
; CHECK-LABEL: func39:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(, %s11)
-; CHECK-NEXT: sla.w.sx %s0, %s0, 31
-; CHECK-NEXT: sra.w.sx %s0, %s0, 31
+; CHECK-NEXT: sll %s0, %s0, 63
+; CHECK-NEXT: sra.l %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
diff --git a/llvm/test/CodeGen/VE/subtraction.ll b/llvm/test/CodeGen/VE/subtraction.ll
index 1bd85d429092..43a30bfe1e1b 100644
--- a/llvm/test/CodeGen/VE/subtraction.ll
+++ b/llvm/test/CodeGen/VE/subtraction.ll
@@ -3,9 +3,11 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i8 %0, %1
ret i8 %3
@@ -14,9 +16,11 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i16 %0, %1
ret i16 %3
@@ -25,6 +29,8 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub nsw i32 %0, %1
@@ -43,6 +49,8 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -53,6 +61,8 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -63,6 +73,8 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i32 %0, %1
@@ -81,9 +93,10 @@ define i64 @func9(i64 %0, i64 %1) {
define signext i8 @func13(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 24
-; CHECK-NEXT: sra.w.sx %s0, %s0, 24
+; CHECK-NEXT: sll %s0, %s0, 56
+; CHECK-NEXT: sra.l %s0, %s0, 56
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i8 %0, -5
ret i8 %3
@@ -92,9 +105,10 @@ define signext i8 @func13(i8 signext %0, i8 signext %1) {
define signext i16 @func14(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
-; CHECK-NEXT: sla.w.sx %s0, %s0, 16
-; CHECK-NEXT: sra.w.sx %s0, %s0, 16
+; CHECK-NEXT: sll %s0, %s0, 48
+; CHECK-NEXT: sra.l %s0, %s0, 48
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i16 %0, -5
ret i16 %3
@@ -103,6 +117,7 @@ define signext i16 @func14(i16 signext %0, i16 signext %1) {
define i32 @func15(i32 %0, i32 %1) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i32 %0, -5
@@ -121,6 +136,7 @@ define i64 @func16(i64 %0, i64 %1) {
define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -131,6 +147,7 @@ define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -141,6 +158,7 @@ define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) {
define i32 @func20(i32 %0, i32 %1) {
; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i32 %0, -5
diff --git a/llvm/test/CodeGen/VE/truncstore.ll b/llvm/test/CodeGen/VE/truncstore.ll
index 357cc6b11791..97a4da4cd93b 100644
--- a/llvm/test/CodeGen/VE/truncstore.ll
+++ b/llvm/test/CodeGen/VE/truncstore.ll
@@ -33,7 +33,6 @@ define void @func2(i8 signext %p, i32* %a) {
define void @func3(i8 signext %p, i64* %a) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i8 %p to i64
@@ -54,7 +53,6 @@ define void @func5(i16 signext %p, i32* %a) {
define void @func6(i16 signext %p, i64* %a) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (, %s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i16 %p to i64
diff --git a/llvm/test/CodeGen/VE/va_caller.ll b/llvm/test/CodeGen/VE/va_caller.ll
index 345ab80867f1..b43ce999c589 100644
--- a/llvm/test/CodeGen/VE/va_caller.ll
+++ b/llvm/test/CodeGen/VE/va_caller.ll
@@ -6,38 +6,36 @@ define i32 @caller() {
; CHECK-LABEL: caller:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill
-; CHECK-NEXT: or %s7, 0, (0)1
-; CHECK-NEXT: st %s7, 280(, %s11)
+; CHECK-NEXT: or %s18, 0, (0)1
+; CHECK-NEXT: st %s18, 280(, %s11)
; CHECK-NEXT: or %s0, 11, (0)1
; CHECK-NEXT: st %s0, 272(, %s11)
-; CHECK-NEXT: st %s7, 264(, %s11)
+; CHECK-NEXT: st %s18, 264(, %s11)
; CHECK-NEXT: or %s0, 10, (0)1
; CHECK-NEXT: st %s0, 256(, %s11)
; CHECK-NEXT: lea.sl %s0, 1075970048
; CHECK-NEXT: st %s0, 248(, %s11)
; CHECK-NEXT: or %s0, 8, (0)1
; CHECK-NEXT: st %s0, 240(, %s11)
-; CHECK-NEXT: st %s7, 232(, %s11)
-; CHECK-NEXT: lea %s0, 1086324736
-; CHECK-NEXT: stl %s0, 228(, %s11)
+; CHECK-NEXT: st %s18, 232(, %s11)
; CHECK-NEXT: or %s5, 5, (0)1
-; CHECK-NEXT: stl %s5, 216(, %s11)
+; CHECK-NEXT: st %s5, 216(, %s11)
; CHECK-NEXT: or %s4, 4, (0)1
-; CHECK-NEXT: stl %s4, 208(, %s11)
+; CHECK-NEXT: st %s4, 208(, %s11)
; CHECK-NEXT: or %s3, 3, (0)1
-; CHECK-NEXT: stl %s3, 200(, %s11)
+; CHECK-NEXT: st %s3, 200(, %s11)
; CHECK-NEXT: or %s2, 2, (0)1
-; CHECK-NEXT: stl %s2, 192(, %s11)
+; CHECK-NEXT: st %s2, 192(, %s11)
; CHECK-NEXT: or %s1, 1, (0)1
-; CHECK-NEXT: stl %s1, 184(, %s11)
-; CHECK-NEXT: or %s18, 0, (0)1
+; CHECK-NEXT: st %s1, 184(, %s11)
+; CHECK-NEXT: st %s18, 176(, %s11)
+; CHECK-NEXT: lea.sl %s6, 1086324736
; CHECK-NEXT: lea %s0, func at lo
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s12, func at hi(, %s0)
-; CHECK-NEXT: lea.sl %s6, 1086324736
-; CHECK-NEXT: stl %s18, 176(, %s11)
+; CHECK-NEXT: st %s6, 224(, %s11)
; CHECK-NEXT: or %s0, 0, %s18
-; CHECK-NEXT: # kill: def $sf6 killed $sf6 killed $sx6
+; CHECK-NEXT: or %s7, 0, %s18
; CHECK-NEXT: bsic %s10, (, %s12)
; CHECK-NEXT: or %s0, 0, %s18
; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/VE/xor.ll b/llvm/test/CodeGen/VE/xor.ll
index d1701f6ef501..b3336bb72ff5 100644
--- a/llvm/test/CodeGen/VE/xor.ll
+++ b/llvm/test/CodeGen/VE/xor.ll
@@ -21,7 +21,9 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, 5, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i8 %a, 5
ret i8 %res
@@ -30,8 +32,10 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: xor %s0, %s0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i8 -5, %a
ret i8 %res
@@ -58,7 +62,9 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i16 %a, 65535
ret i16 %res
@@ -67,7 +73,9 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (52)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i16 4095, %a
ret i16 %res
@@ -94,7 +102,9 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (36)0
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i32 %a, 268435455
ret i32 %res
@@ -103,7 +113,9 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (36)0
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i32 %a, 268435455
ret i32 %res
@@ -112,6 +124,7 @@ define zeroext i32 @funci32z(i32 zeroext %a) {
define i32 @funci32_another(i32 %0) {
; CHECK-LABEL: funci32_another:
; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (33)1
; CHECK-NEXT: or %s11, 0, %s9
%2 = xor i32 %0, -2147483648
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