[llvm] 47a4a27 - Upgrade MC to v0.9.
Hsiangkai Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 16:42:44 PDT 2020
Author: Hsiangkai Wang
Date: 2020-08-01T07:42:06+08:00
New Revision: 47a4a27f47203055a4700b65533262409f83c491
URL: https://github.com/llvm/llvm-project/commit/47a4a27f47203055a4700b65533262409f83c491
DIFF: https://github.com/llvm/llvm-project/commit/47a4a27f47203055a4700b65533262409f83c491.diff
LOG: Upgrade MC to v0.9.
Differential revision: https://reviews.llvm.org/D80802
Added:
llvm/test/MC/RISCV/rvv/ext.s
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/compare.s
llvm/test/MC/RISCV/rvv/convert.s
llvm/test/MC/RISCV/rvv/fcompare.s
llvm/test/MC/RISCV/rvv/fothers.s
llvm/test/MC/RISCV/rvv/freduction.s
llvm/test/MC/RISCV/rvv/invalid.s
llvm/test/MC/RISCV/rvv/load.s
llvm/test/MC/RISCV/rvv/mask.s
llvm/test/MC/RISCV/rvv/reduction.s
llvm/test/MC/RISCV/rvv/snippet.s
llvm/test/MC/RISCV/rvv/store.s
llvm/test/MC/RISCV/rvv/vsetvl.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 407f980bd35e..c094163c2f9d 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -288,11 +288,21 @@ struct RISCVOperand : public MCParsedAsmOperand {
SEW_1024,
};
- enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 };
+ enum class VLMUL {
+ LMUL_1 = 0,
+ LMUL_2,
+ LMUL_4,
+ LMUL_8,
+ LMUL_F8 = 5,
+ LMUL_F4,
+ LMUL_F2
+ };
struct VTypeOp {
VSEW Sew;
VLMUL Lmul;
+ bool TailAgnostic;
+ bool MaskedoffAgnostic;
unsigned Encoding;
};
@@ -763,7 +773,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
case VSEW::SEW_1024:
return "e1024";
}
- return "";
+ llvm_unreachable("Unknown SEW.");
}
static StringRef getLMULStr(VLMUL Lmul) {
@@ -776,8 +786,14 @@ struct RISCVOperand : public MCParsedAsmOperand {
return "m4";
case VLMUL::LMUL_8:
return "m8";
+ case VLMUL::LMUL_F2:
+ return "mf2";
+ case VLMUL::LMUL_F4:
+ return "mf4";
+ case VLMUL::LMUL_F8:
+ return "mf8";
}
- return "";
+ llvm_unreachable("Unknown LMUL.");
}
StringRef getVType(SmallString<32> &Buf) const {
@@ -852,15 +868,31 @@ struct RISCVOperand : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<RISCVOperand> createVType(APInt Sew, APInt Lmul,
- SMLoc S, bool IsRV64) {
+ static std::unique_ptr<RISCVOperand>
+ createVType(APInt Sew, APInt Lmul, bool Fractional, bool TailAgnostic,
+ bool MaskedoffAgnostic, SMLoc S, bool IsRV64) {
auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
Sew.ashrInPlace(3);
unsigned SewLog2 = Sew.logBase2();
unsigned LmulLog2 = Lmul.logBase2();
Op->VType.Sew = static_cast<VSEW>(SewLog2);
- Op->VType.Lmul = static_cast<VLMUL>(LmulLog2);
- Op->VType.Encoding = (SewLog2 << 2) | LmulLog2;
+ if (Fractional) {
+ unsigned Flmul = 8 - LmulLog2;
+ Op->VType.Lmul = static_cast<VLMUL>(Flmul);
+ Op->VType.Encoding =
+ ((Flmul & 0x4) << 3) | ((SewLog2 & 0x7) << 2) | (Flmul & 0x3);
+ } else {
+ Op->VType.Lmul = static_cast<VLMUL>(LmulLog2);
+ Op->VType.Encoding = (SewLog2 << 2) | LmulLog2;
+ }
+ if (TailAgnostic) {
+ Op->VType.Encoding |= 0x40;
+ }
+ if (MaskedoffAgnostic) {
+ Op->VType.Encoding |= 0x80;
+ }
+ Op->VType.TailAgnostic = TailAgnostic;
+ Op->VType.MaskedoffAgnostic = MaskedoffAgnostic;
Op->StartLoc = S;
Op->IsRV64 = IsRV64;
return Op;
@@ -1181,8 +1213,10 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
case Match_InvalidVTypeI: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
- return Error(ErrorLoc,
- "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]");
+ return Error(
+ ErrorLoc,
+ "operand must be "
+ "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
}
case Match_InvalidVMaskRegister: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
@@ -1549,7 +1583,7 @@ OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
if (getLexer().getKind() != AsmToken::Identifier)
return MatchOperand_NoMatch;
- // Parse "e8,m1"
+ // Parse "e8,m1,t[a|u],m[a|u]"
StringRef Name = getLexer().getTok().getIdentifier();
if (!Name.consume_front("e"))
return MatchOperand_NoMatch;
@@ -1559,13 +1593,6 @@ OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
return MatchOperand_NoMatch;
getLexer().Lex();
- if (getLexer().getKind() == AsmToken::EndOfStatement) {
- Operands.push_back(
- RISCVOperand::createVType(Sew, APInt(16, 1), S, isRV64()));
-
- return MatchOperand_Success;
- }
-
if (!getLexer().is(AsmToken::Comma))
return MatchOperand_NoMatch;
getLexer().Lex();
@@ -1573,15 +1600,51 @@ OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
Name = getLexer().getTok().getIdentifier();
if (!Name.consume_front("m"))
return MatchOperand_NoMatch;
+ // "m" or "mf"
+ bool Fractional = false;
+ if (Name.consume_front("f")) {
+ Fractional = true;
+ }
APInt Lmul(16, Name, 10);
if (Lmul != 1 && Lmul != 2 && Lmul != 4 && Lmul != 8)
return MatchOperand_NoMatch;
getLexer().Lex();
+ if (!getLexer().is(AsmToken::Comma))
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ Name = getLexer().getTok().getIdentifier();
+ // ta or tu
+ bool TailAgnostic;
+ if (Name.consume_front("ta"))
+ TailAgnostic = true;
+ else if (Name.consume_front("tu"))
+ TailAgnostic = false;
+ else
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ if (!getLexer().is(AsmToken::Comma))
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ Name = getLexer().getTok().getIdentifier();
+ // ma or mu
+ bool MaskedoffAgnostic;
+ if (Name.consume_front("ma"))
+ MaskedoffAgnostic = true;
+ else if (Name.consume_front("mu"))
+ MaskedoffAgnostic = false;
+ else
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
if (getLexer().getKind() != AsmToken::EndOfStatement)
return MatchOperand_NoMatch;
- Operands.push_back(RISCVOperand::createVType(Sew, Lmul, S, isRV64()));
+ Operands.push_back(RISCVOperand::createVType(
+ Sew, Lmul, Fractional, TailAgnostic, MaskedoffAgnostic, S, isRV64()));
return MatchOperand_Success;
}
@@ -2281,71 +2344,41 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
return false;
unsigned DestReg = Inst.getOperand(0).getReg();
+ unsigned CheckReg;
// Operands[1] will be the first operand, DestReg.
SMLoc Loc = Operands[1]->getStartLoc();
- if ((TargetFlags == RISCV::WidenV) || (TargetFlags == RISCV::WidenW) ||
- (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather) ||
- (TargetFlags == RISCV::Vcompress)) {
- if (TargetFlags != RISCV::WidenW) {
- unsigned Src2Reg = Inst.getOperand(1).getReg();
- if (DestReg == Src2Reg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
- if (TargetFlags == RISCV::WidenV) {
- // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg + 1 == Src2Reg)
- return Error(Loc,
- "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
- }
- if (Inst.getOperand(2).isReg()) {
- unsigned Src1Reg = Inst.getOperand(2).getReg();
- if (DestReg == Src1Reg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
- if (TargetFlags == RISCV::WidenV || TargetFlags == RISCV::WidenW) {
- // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg + 1 == Src1Reg)
- return Error(Loc,
- "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
- }
- if (Inst.getNumOperands() == 4) {
- unsigned MaskReg = Inst.getOperand(3).getReg();
-
- if (DestReg == MaskReg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the mask register.");
- }
- } else if (TargetFlags == RISCV::Narrow) {
- unsigned Src2Reg = Inst.getOperand(1).getReg();
- if (DestReg == Src2Reg)
+ if (TargetFlags & RISCV::VS2Constraint) {
+ CheckReg = Inst.getOperand(1).getReg();
+ if (DestReg == CheckReg)
return Error(Loc, "The destination vector register group cannot overlap"
" the source vector register group.");
- // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg == Src2Reg + 1)
+ }
+ if ((TargetFlags & RISCV::VS1Constraint) && (Inst.getOperand(2).isReg())) {
+ CheckReg = Inst.getOperand(2).getReg();
+ if (DestReg == CheckReg)
return Error(Loc, "The destination vector register group cannot overlap"
" the source vector register group.");
- } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::Iota) {
- unsigned Src2Reg = Inst.getOperand(1).getReg();
- if (DestReg == Src2Reg)
+ }
+ if ((TargetFlags & RISCV::VMConstraint) && (DestReg == RISCV::V0)) {
+ // vadc, vsbc are special cases. These instructions have no mask register.
+ // The destination register could not be V0.
+ unsigned Opcode = Inst.getOpcode();
+ if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM ||
+ Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM ||
+ Opcode == RISCV::VSBC_VXM)
+ return Error(Loc, "The destination vector register group cannot be V0.");
+
+ // Regardless masked or unmasked version, the number of operands is the
+ // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
+ // actually. We need to check the last operand to ensure whether it is
+ // masked or not.
+ if ((TargetFlags & RISCV::OneInput) && (Inst.getNumOperands() == 3))
+ CheckReg = Inst.getOperand(2).getReg();
+ else if (Inst.getNumOperands() == 4)
+ CheckReg = Inst.getOperand(3).getReg();
+ if (DestReg == CheckReg)
return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
- if (TargetFlags == RISCV::WidenCvt) {
- // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
- if (DestReg + 1 == Src2Reg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the source vector register group.");
- }
- if (Inst.getNumOperands() == 3) {
- unsigned MaskReg = Inst.getOperand(2).getReg();
-
- if (DestReg == MaskReg)
- return Error(Loc, "The destination vector register group cannot overlap"
- " the mask register.");
- }
+ " the mask register.");
}
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index eae3e13dbe40..2c7038a0a8ac 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -155,10 +155,28 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
unsigned Imm = MI->getOperand(OpNo).getImm();
unsigned Sew = (Imm >> 2) & 0x7;
unsigned Lmul = Imm & 0x3;
+ bool Fractional = (Imm >> 5) & 0x1;
- Lmul = 0x1 << Lmul;
Sew = 0x1 << (Sew + 3);
- O << "e" << Sew << ",m" << Lmul;
+ O << "e" << Sew;
+ if (Fractional) {
+ Lmul = 4 - Lmul;
+ Lmul = 0x1 << Lmul;
+ O << ",mf" << Lmul;
+ } else {
+ Lmul = 0x1 << Lmul;
+ O << ",m" << Lmul;
+ }
+ bool TailAgnostic = Imm & 0x40;
+ bool MaskedoffAgnostic = Imm & 0x80;
+ if (TailAgnostic)
+ O << ",ta";
+ else
+ O << ",tu";
+ if (MaskedoffAgnostic)
+ O << ",ma";
+ else
+ O << ",mu";
}
void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index a47945a6a515..21f051414635 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -52,15 +52,37 @@ def InstFormatOther : InstFormat<17>;
class RISCVVConstraint<bits<4> val> {
bits<4> Value = val;
}
-def NoConstraint : RISCVVConstraint<0>;
-def WidenV : RISCVVConstraint<1>;
-def WidenW : RISCVVConstraint<2>;
-def WidenCvt : RISCVVConstraint<3>;
-def Narrow : RISCVVConstraint<4>;
-def Iota : RISCVVConstraint<5>;
-def SlideUp : RISCVVConstraint<6>;
-def Vrgather : RISCVVConstraint<7>;
-def Vcompress : RISCVVConstraint<8>;
+def NoConstraint : RISCVVConstraint<0b0000>;
+def VS2Constraint : RISCVVConstraint<0b0001>;
+def VS1Constraint : RISCVVConstraint<0b0010>;
+def VMConstraint : RISCVVConstraint<0b0100>;
+def OneInput : RISCVVConstraint<0b1000>;
+
+def WidenV : RISCVVConstraint<!or(VS2Constraint.Value,
+ VS1Constraint.Value,
+ VMConstraint.Value)>;
+def WidenW : RISCVVConstraint<!or(VS1Constraint.Value,
+ VMConstraint.Value)>;
+def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value,
+ VMConstraint.Value,
+ OneInput.Value)>;
+def Narrow : RISCVVConstraint<!or(VS2Constraint.Value,
+ VMConstraint.Value)>;
+def NarrowCvt : RISCVVConstraint<!or(VS2Constraint.Value,
+ VMConstraint.Value,
+ OneInput.Value)>;
+def Vmadc : RISCVVConstraint<!or(VS2Constraint.Value,
+ VS1Constraint.Value)>;
+def Iota : RISCVVConstraint<!or(VS2Constraint.Value,
+ VMConstraint.Value,
+ OneInput.Value)>;
+def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value,
+ VMConstraint.Value)>;
+def Vrgather : RISCVVConstraint<!or(VS2Constraint.Value,
+ VS1Constraint.Value,
+ VMConstraint.Value)>;
+def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value,
+ VS1Constraint.Value)>;
// The following opcode names match those given in Table 19.1 in the
// RISC-V User-level ISA specification ("RISC-V base opcode map").
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index e5f154966ba6..8ca010d033c3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -21,20 +21,17 @@ def OPIVX : RISCVVFormat<0b100>;
def OPFVF : RISCVVFormat<0b101>;
def OPMVX : RISCVVFormat<0b110>;
-class RISCVMOP<bits<3> val> {
- bits<3> Value = val;
+class RISCVMOP<bits<2> val> {
+ bits<2> Value = val;
}
-def MOPLDUnitStrideU : RISCVMOP<0b000>;
-def MOPLDStridedU : RISCVMOP<0b010>;
-def MOPLDIndexedU : RISCVMOP<0b011>;
-def MOPLDUnitStrideS : RISCVMOP<0b100>;
-def MOPLDStridedS : RISCVMOP<0b110>;
-def MOPLDIndexedS : RISCVMOP<0b111>;
-
-def MOPSTUnitStride : RISCVMOP<0b000>;
-def MOPSTStrided : RISCVMOP<0b010>;
-def MOPSTIndexedOrder: RISCVMOP<0b011>;
-def MOPSTIndexedUnOrd: RISCVMOP<0b111>;
+def MOPLDUnitStride : RISCVMOP<0b00>;
+def MOPLDStrided : RISCVMOP<0b10>;
+def MOPLDIndexed : RISCVMOP<0b11>;
+
+def MOPSTUnitStride : RISCVMOP<0b00>;
+def MOPSTIndexedUnord : RISCVMOP<0b01>;
+def MOPSTStrided : RISCVMOP<0b10>;
+def MOPSTIndexedOrder : RISCVMOP<0b11>;
class RISCVLSUMOP<bits<5> val> {
bits<5> Value = val;
@@ -45,13 +42,17 @@ def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
def SUMOPUnitStride : RISCVLSUMOP<0b00000>;
def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
-class RISCVWidth<bits<3> val> {
- bits<3> Value = val;
+class RISCVWidth<bits<4> val> {
+ bits<4> Value = val;
}
-def LSWidthVByte : RISCVWidth<0b000>;
-def LSWidthVHalf : RISCVWidth<0b101>;
-def LSWidthVWord : RISCVWidth<0b110>;
-def LSWidthVSEW : RISCVWidth<0b111>;
+def LSWidth8 : RISCVWidth<0b0000>;
+def LSWidth16 : RISCVWidth<0b0101>;
+def LSWidth32 : RISCVWidth<0b0110>;
+def LSWidth64 : RISCVWidth<0b0111>;
+def LSWidth128 : RISCVWidth<0b1000>;
+def LSWidth256 : RISCVWidth<0b1101>;
+def LSWidth512 : RISCVWidth<0b1110>;
+def LSWidth1024 : RISCVWidth<0b1111>;
class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
@@ -103,6 +104,7 @@ class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
let Opcode = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
@@ -122,6 +124,7 @@ class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
let Opcode = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
@@ -140,6 +143,7 @@ class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
let Opcode = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
@@ -159,6 +163,7 @@ class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
let Opcode = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
@@ -177,10 +182,11 @@ class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
let Opcode = OPC_OP_V.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
-class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
- RISCVWidth width, dag outs, dag ins, string opcodestr,
+class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
+ bits<3> width, dag outs, dag ins, string opcodestr,
string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
@@ -188,18 +194,20 @@ class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = MOPLDUnitStride.Value;
let Inst{25} = vm;
let Inst{24-20} = lumop.Value;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vd;
let Opcode = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
-class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs2;
@@ -208,18 +216,20 @@ class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = MOPLDStrided.Value;
let Inst{25} = vm;
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vd;
let Opcode = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
-class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> vs2;
@@ -228,19 +238,21 @@ class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = MOPLDIndexed.Value;
let Inst{25} = vm;
let Inst{24-20} = vs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vd;
let Opcode = OPC_LOAD_FP.Value;
let Uses = [VTYPE, VL];
+ let RVVConstraint = VMConstraint;
}
-class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
- RISCVWidth width, dag outs, dag ins, string opcodestr,
+class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
+ bits<3> width, dag outs, dag ins, string opcodestr,
string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
@@ -248,18 +260,19 @@ class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = MOPSTUnitStride.Value;
let Inst{25} = vm;
let Inst{24-20} = sumop.Value;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vs3;
let Opcode = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs2;
@@ -268,18 +281,19 @@ class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = MOPSTStrided.Value;
let Inst{25} = vm;
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vs3;
let Opcode = OPC_STORE_FP.Value;
let Uses = [VTYPE, VL];
}
-class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> vs2;
@@ -288,11 +302,12 @@ class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
bit vm;
let Inst{31-29} = nf;
- let Inst{28-26} = mop.Value;
+ let Inst{28} = mew;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
let Inst{24-20} = vs2;
let Inst{19-15} = rs1;
- let Inst{14-12} = width.Value;
+ let Inst{14-12} = width;
let Inst{11-7} = vs3;
let Opcode = OPC_STORE_FP.Value;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 21bc508cdc9c..cd8b6d5fba59 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -138,14 +138,53 @@ namespace RISCV {
// Match with the definitions in RISCVInstrFormatsV.td
enum RVVConstraintType {
NoConstraint = 0,
- WidenV = 1,
- WidenW = 2,
- WidenCvt = 3,
- Narrow = 4,
- Iota = 5,
- SlideUp = 6,
- Vrgather = 7,
- Vcompress = 8,
+ VS2Constraint = 0b0001,
+ VS1Constraint = 0b0010,
+ VMConstraint = 0b0100,
+ OneInput = 0b1000,
+
+ // Illegal instructions:
+ //
+ // * The destination vector register group for a masked vector instruction
+ // cannot overlap the source mask register (v0), unless the destination vector
+ // register is being written with a mask value (e.g., comparisons) or the
+ // scalar result of a reduction.
+ //
+ // * Widening: The destination vector register group cannot overlap a source
+ // vector register group of a
diff erent EEW
+ //
+ // * Narrowing: The destination vector register group cannot overlap the
+ // first source vector register group
+ //
+ // * For vadc and vsbc, an illegal instruction exception is raised if the
+ // destination vector register is v0.
+ //
+ // * For vmadc and vmsbc, an illegal instruction exception is raised if the
+ // destination vector register overlaps a source vector register group.
+ //
+ // * viota: An illegal instruction exception is raised if the destination
+ // vector register group overlaps the source vector mask register. If the
+ // instruction is masked, an illegal instruction exception is issued if the
+ // destination vector register group overlaps v0.
+ //
+ // * v[f]slide[1]up: The destination vector register group for vslideup cannot
+ // overlap the source vector register group.
+ //
+ // * vrgather: The destination vector register group cannot overlap with the
+ // source vector register groups.
+ //
+ // * vcompress: The destination vector register group cannot overlap the
+ // source vector register group or the source mask register
+ WidenV = VS2Constraint | VS1Constraint | VMConstraint,
+ WidenW = VS1Constraint | VMConstraint,
+ WidenCvt = VS2Constraint | VMConstraint | OneInput,
+ Narrow = VS2Constraint | VMConstraint,
+ NarrowCvt = VS2Constraint | VMConstraint | OneInput,
+ Vmadc = VS2Constraint | VS1Constraint,
+ Iota = VS2Constraint | VMConstraint | OneInput,
+ SlideUp = VS2Constraint | VMConstraint,
+ Vrgather = VS2Constraint | VS1Constraint | VMConstraint,
+ Vcompress = VS2Constraint | VS1Constraint,
ConstraintOffset = 5,
ConstraintMask = 0b1111
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 1c7f53fecb8c..ae335ddce882 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
///
/// This file describes the RISC-V instructions from the standard 'V' Vector
-/// extension, version 0.8.
+/// extension, version 0.9.
/// This version is still experimental as the 'V' extension hasn't been
/// ratified yet.
///
@@ -96,27 +96,30 @@ def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
// load vd, (rs1), vm
-class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
- string opcodestr>
- : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd),
+class VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width,
+ string opcodestr>
+ : RVInstVLU<0b000, width.Value{3}, lumop, width.Value{2-0},
+ (outs VRegOp:$vd),
(ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
// load vd, (rs1), rs2, vm
-class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd),
+class VStridedLoad<RISCVWidth width, string opcodestr>
+ : RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
+ (outs VRegOp:$vd),
(ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $rs2$vm">;
// load vd, (rs1), vs2, vm
-class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd),
+class VIndexedLoad<RISCVWidth width, string opcodestr>
+ : RVInstVLX<0b000, width.Value{3}, width.Value{2-0},
+ (outs VRegOp:$vd),
(ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $vs2$vm">;
// vl<nf>r.v vd, (rs1)
class VWholeLoad<bits<3> nf, string opcodestr>
- : RVInstVLU<nf, MOPLDUnitStrideU, LUMOPUnitStrideWholeReg,
- LSWidthVSEW, (outs VRegOp:$vd), (ins GPR:$rs1),
+ : RVInstVLU<nf, 0b0, LUMOPUnitStrideWholeReg,
+ 0b000, (outs VRegOp:$vd), (ins GPR:$rs1),
opcodestr, "$vd, (${rs1})"> {
let vm = 1;
let Uses = [];
@@ -125,28 +128,28 @@ class VWholeLoad<bits<3> nf, string opcodestr>
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
// store vd, vs3, (rs1), vm
-class VUnitStrideStore<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
+class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width,
string opcodestr>
- : RVInstVSU<0b000, mop, sumop, width, (outs),
- (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
+ : RVInstVSU<0b000, width.Value{3}, sumop, width.Value{2-0},
+ (outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
"$vs3, (${rs1})$vm">;
// store vd, vs3, (rs1), rs2, vm
-class VStridedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVSS<0b000, mop, width, (outs),
+class VStridedStore<RISCVWidth width, string opcodestr>
+ : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs),
(ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $rs2$vm">;
// store vd, vs3, (rs1), vs2, vm
class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVSX<0b000, mop, width, (outs),
+ : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $vs2$vm">;
// vs<nf>r.v vd, (rs1)
class VWholeStore<bits<3> nf, string opcodestr>
- : RVInstVSU<nf, MOPSTUnitStride, SUMOPUnitStrideWholeReg,
- LSWidthVSEW, (outs), (ins VRegOp:$vs3, GPR:$rs1),
+ : RVInstVSU<nf, 0b0, SUMOPUnitStrideWholeReg,
+ 0b000, (outs), (ins VRegOp:$vs3, GPR:$rs1),
opcodestr, "$vs3, (${rs1})"> {
let vm = 1;
let Uses = [];
@@ -372,68 +375,79 @@ def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
// Vector Unit-Stride Instructions
-def VLB_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVByte, "vlb.v">;
-def VLH_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVHalf, "vlh.v">;
-def VLW_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVWord, "vlw.v">;
-
-def VLBU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVByte, "vlbu.v">;
-def VLHU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVHalf, "vlhu.v">;
-def VLWU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVWord, "vlwu.v">;
-
-def VLE_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVSEW, "vle.v">;
-
-def VLBFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVByte, "vlbff.v">;
-def VLHFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVHalf, "vlhff.v">;
-def VLWFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVWord, "vlwff.v">;
-
-def VLBUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVByte, "vlbuff.v">;
-def VLHUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVHalf, "vlhuff.v">;
-def VLWUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVWord, "vlwuff.v">;
-
-def VLEFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVSEW, "vleff.v">;
-
-def VSB_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVByte, "vsb.v">;
-def VSH_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVHalf, "vsh.v">;
-def VSW_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVWord, "vsw.v">;
-
-def VSE_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVSEW, "vse.v">;
+def VLE8_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth8, "vle8.v">;
+def VLE16_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth16, "vle16.v">;
+def VLE32_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth32, "vle32.v">;
+def VLE64_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth64, "vle64.v">;
+def VLE128_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth128, "vle128.v">;
+def VLE256_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth256, "vle256.v">;
+def VLE512_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth512, "vle512.v">;
+def VLE1024_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth1024, "vle1024.v">;
+
+def VLE8FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth8, "vle8ff.v">;
+def VLE16FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth16, "vle16ff.v">;
+def VLE32FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">;
+def VLE64FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">;
+def VLE128FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth128, "vle128ff.v">;
+def VLE256FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth256, "vle256ff.v">;
+def VLE512FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth512, "vle512ff.v">;
+def VLE1024FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth1024, "vle1024ff.v">;
+
+def VSE8_V : VUnitStrideStore<SUMOPUnitStride, LSWidth8, "vse8.v">;
+def VSE16_V : VUnitStrideStore<SUMOPUnitStride, LSWidth16, "vse16.v">;
+def VSE32_V : VUnitStrideStore<SUMOPUnitStride, LSWidth32, "vse32.v">;
+def VSE64_V : VUnitStrideStore<SUMOPUnitStride, LSWidth64, "vse64.v">;
+def VSE128_V : VUnitStrideStore<SUMOPUnitStride, LSWidth128, "vse128.v">;
+def VSE256_V : VUnitStrideStore<SUMOPUnitStride, LSWidth256, "vse256.v">;
+def VSE512_V : VUnitStrideStore<SUMOPUnitStride, LSWidth512, "vse512.v">;
+def VSE1024_V : VUnitStrideStore<SUMOPUnitStride, LSWidth1024, "vse1024.v">;
// Vector Strided Instructions
-def VLSB_V : VStridedLoad<MOPLDStridedS, LSWidthVByte, "vlsb.v">;
-def VLSH_V : VStridedLoad<MOPLDStridedS, LSWidthVHalf, "vlsh.v">;
-def VLSW_V : VStridedLoad<MOPLDStridedS, LSWidthVWord, "vlsw.v">;
-
-def VLSBU_V : VStridedLoad<MOPLDStridedU, LSWidthVByte, "vlsbu.v">;
-def VLSHU_V : VStridedLoad<MOPLDStridedU, LSWidthVHalf, "vlshu.v">;
-def VLSWU_V : VStridedLoad<MOPLDStridedU, LSWidthVWord, "vlswu.v">;
-
-def VLSE_V : VStridedLoad<MOPLDStridedU, LSWidthVSEW, "vlse.v">;
-
-def VSSB_V : VStridedStore<MOPSTStrided, LSWidthVByte, "vssb.v">;
-def VSSH_V : VStridedStore<MOPSTStrided, LSWidthVHalf, "vssh.v">;
-def VSSW_V : VStridedStore<MOPSTStrided, LSWidthVWord, "vssw.v">;
-def VSSE_V : VStridedStore<MOPSTStrided, LSWidthVSEW, "vsse.v">;
+def VLSE8_V : VStridedLoad<LSWidth8, "vlse8.v">;
+def VLSE16_V : VStridedLoad<LSWidth16, "vlse16.v">;
+def VLSE32_V : VStridedLoad<LSWidth32, "vlse32.v">;
+def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">;
+def VLSE128_V : VStridedLoad<LSWidth128, "vlse128.v">;
+def VLSE256_V : VStridedLoad<LSWidth256, "vlse256.v">;
+def VLSE512_V : VStridedLoad<LSWidth512, "vlse512.v">;
+def VLSE1024_V : VStridedLoad<LSWidth1024, "vlse1024.v">;
+
+def VSSE8_V : VStridedStore<LSWidth8, "vsse8.v">;
+def VSSE16_V : VStridedStore<LSWidth16, "vsse16.v">;
+def VSSE32_V : VStridedStore<LSWidth32, "vsse32.v">;
+def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">;
+def VSSE128_V : VStridedStore<LSWidth128, "vsse128.v">;
+def VSSE256_V : VStridedStore<LSWidth256, "vsse256.v">;
+def VSSE512_V : VStridedStore<LSWidth512, "vsse512.v">;
+def VSSE1024_V : VStridedStore<LSWidth1024, "vsse1024.v">;
// Vector Indexed Instructions
-def VLXB_V : VIndexedLoad<MOPLDIndexedS, LSWidthVByte, "vlxb.v">;
-def VLXH_V : VIndexedLoad<MOPLDIndexedS, LSWidthVHalf, "vlxh.v">;
-def VLXW_V : VIndexedLoad<MOPLDIndexedS, LSWidthVWord, "vlxw.v">;
-
-def VLXBU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVByte, "vlxbu.v">;
-def VLXHU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVHalf, "vlxhu.v">;
-def VLXWU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVWord, "vlxwu.v">;
-
-def VLXE_V : VIndexedLoad<MOPLDIndexedU, LSWidthVSEW, "vlxe.v">;
-
-def VSXB_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVByte, "vsxb.v">;
-def VSXH_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVHalf, "vsxh.v">;
-def VSXW_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVWord, "vsxw.v">;
-def VSXE_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVSEW, "vsxe.v">;
-
-def VSUXB_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVByte, "vsuxb.v">;
-def VSUXH_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVHalf, "vsuxh.v">;
-def VSUXW_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVWord, "vsuxw.v">;
-def VSUXE_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVSEW, "vsuxe.v">;
+def VLXEI8_V : VIndexedLoad<LSWidth8, "vlxei8.v">;
+def VLXEI16_V : VIndexedLoad<LSWidth16, "vlxei16.v">;
+def VLXEI32_V : VIndexedLoad<LSWidth32, "vlxei32.v">;
+def VLXEI64_V : VIndexedLoad<LSWidth64, "vlxei64.v">;
+def VLXEI128_V : VIndexedLoad<LSWidth128, "vlxei128.v">;
+def VLXEI256_V : VIndexedLoad<LSWidth256, "vlxei256.v">;
+def VLXEI512_V : VIndexedLoad<LSWidth512, "vlxei512.v">;
+def VLXEI1024_V : VIndexedLoad<LSWidth1024, "vlxei1024.v">;
+
+def VSXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsxei8.v">;
+def VSXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsxei16.v">;
+def VSXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsxei32.v">;
+def VSXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsxei64.v">;
+def VSXEI128_V : VIndexedStore<MOPSTIndexedOrder, LSWidth128, "vsxei128.v">;
+def VSXEI256_V : VIndexedStore<MOPSTIndexedOrder, LSWidth256, "vsxei256.v">;
+def VSXEI512_V : VIndexedStore<MOPSTIndexedOrder, LSWidth512, "vsxei512.v">;
+def VSXEI1024_V : VIndexedStore<MOPSTIndexedOrder, LSWidth1024, "vsxei1024.v">;
+
+def VSUXEI8_V : VIndexedStore<MOPSTIndexedUnord, LSWidth8, "vsuxei8.v">;
+def VSUXEI16_V : VIndexedStore<MOPSTIndexedUnord, LSWidth16, "vsuxei16.v">;
+def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
+def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
+def VSUXEI128_V : VIndexedStore<MOPSTIndexedUnord, LSWidth128, "vsuxei128.v">;
+def VSUXEI256_V : VIndexedStore<MOPSTIndexedUnord, LSWidth256, "vsuxei256.v">;
+def VSUXEI512_V : VIndexedStore<MOPSTIndexedUnord, LSWidth512, "vsuxei512.v">;
+def VSUXEI1024_V : VIndexedStore<MOPSTIndexedUnord, LSWidth1024, "vsuxei1024.v">;
def VL1R_V : VWholeLoad<0, "vl1r.v">;
def VS1R_V : VWholeStore<0, "vs1r.v">;
@@ -472,13 +486,25 @@ def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
(VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
+// Vector Integer Extension
+defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>;
+defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>;
+defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>;
+defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>;
+defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>;
+defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>;
+
// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
// Vector Bitwise Logical Instructions
defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
@@ -504,6 +530,7 @@ defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
// Vector Integer Comparison Instructions
+let RVVConstraint = NoConstraint in {
defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>;
defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>;
defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>;
@@ -512,6 +539,7 @@ defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>;
defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>;
defm VMSGTU_V : VALU_IV_X_I<"vmsgtu", 0b011110>;
defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>;
+} // RVVConstraint = NoConstraint
def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm",
(VMSLTU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
@@ -664,7 +692,7 @@ defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
// Vector Floating-Point Square-Root Instruction
-defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
// Vector Floating-Point MIN/MAX Instructions
defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
@@ -676,12 +704,14 @@ defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
// Vector Floating-Point Compare Instructions
+let RVVConstraint = NoConstraint in {
defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>;
defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>;
defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>;
defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
+} // RVVConstraint = NoConstraint
def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
(VMFLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
@@ -689,7 +719,7 @@ def : InstAlias<"vmfge.vv $vd, $va, $vb$vm",
(VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
// Vector Floating-Point Classify Instruction
-defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
// Vector Floating-Point Merge Instruction
@@ -708,31 +738,38 @@ def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
// Single-Width Floating-Point/Integer Type-Convert Instructions
-defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
-defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
-defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
-defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
+defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;
+defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
+defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
+defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>;
+defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>;
// Widening Floating-Point/Integer Type-Convert Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in {
-defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
-defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
-defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
-defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
-defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>;
+defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>;
+defm VFWCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>;
+defm VFWCVT_RTZ_X_F_V : VALU_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
+defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>;
+defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>;
+defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
// Narrowing Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
-defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>;
-defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>;
-defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>;
-defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>;
-defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>;
-defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+let Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt in {
+defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>;
+defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>;
+defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>;
+defm VFNCVT_RTZ_X_F_W : VALU_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>;
+defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>;
+defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>;
+defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>;
+defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt
// Vector Single-Width Integer Reduction Instructions
+let RVVConstraint = NoConstraint in {
defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>;
defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>;
defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>;
@@ -741,32 +778,35 @@ defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>;
defm VREDAND : VALU_MV_V<"vredand", 0b000001>;
defm VREDOR : VALU_MV_V<"vredor", 0b000010>;
defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>;
+} // RVVConstraint = NoConstraint
// Vector Widening Integer Reduction Instructions
-let Constraints = "@earlyclobber $vd" in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>;
defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>;
-} // Constraints = "@earlyclobber $vd"
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
// Vector Single-Width Floating-Point Reduction Instructions
+let RVVConstraint = NoConstraint in {
defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>;
defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>;
defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>;
defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>;
+} // RVVConstraint = NoConstraint
// Vector Widening Floating-Point Reduction Instructions
-let Constraints = "@earlyclobber $vd" in {
+let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
// Set earlyclobber for following instructions for second and mask operands.
// This has the downside that the earlyclobber constraint is too coarse and
// will impose unnecessary restrictions by not allowing the destination to
// overlap with the first (wide) operand.
defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>;
defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>;
-} // Constraints = "@earlyclobber $vd"
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
// Vector Mask-Register Logical Instructions
defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">;
@@ -778,7 +818,7 @@ defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">;
defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
-def : InstAlias<"vmcpy.m $vd, $vs",
+def : InstAlias<"vmmv.m $vd, $vs",
(VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
def : InstAlias<"vmclr.m $vd",
(VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
@@ -847,8 +887,10 @@ defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
+defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
+defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>;
// Vector Register Gather Instruction
let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s
index 7bf452f771a7..f93aeac1796a 100644
--- a/llvm/test/MC/RISCV/rvv/compare.s
+++ b/llvm/test/MC/RISCV/rvv/compare.s
@@ -8,6 +8,12 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+vmslt.vv v0, v4, v20, v0.t
+# CHECK-INST: vmslt.vv v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x00,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 00 4a 6c <unknown>
+
vmseq.vv v8, v4, v20, v0.t
# CHECK-INST: vmseq.vv v8, v4, v20, v0.t
# CHECK-ENCODING: [0x57,0x04,0x4a,0x60]
diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s
index e9f8860e97b5..bc818523e3e9 100644
--- a/llvm/test/MC/RISCV/rvv/convert.s
+++ b/llvm/test/MC/RISCV/rvv/convert.s
@@ -10,180 +10,252 @@
vfcvt.xu.f.v v8, v4, v0.t
# CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x40,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 88 <unknown>
+# CHECK-UNKNOWN: 57 14 40 48 <unknown>
vfcvt.xu.f.v v8, v4
# CHECK-INST: vfcvt.xu.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8a <unknown>
+# CHECK-UNKNOWN: 57 14 40 4a <unknown>
vfcvt.x.f.v v8, v4, v0.t
# CHECK-INST: vfcvt.x.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x40,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x40,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 40 88 <unknown>
+# CHECK-UNKNOWN: 57 94 40 48 <unknown>
vfcvt.x.f.v v8, v4
# CHECK-INST: vfcvt.x.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x40,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x40,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 40 8a <unknown>
+# CHECK-UNKNOWN: 57 94 40 4a <unknown>
vfcvt.f.xu.v v8, v4, v0.t
# CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x41,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x41,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 41 88 <unknown>
+# CHECK-UNKNOWN: 57 14 41 48 <unknown>
vfcvt.f.xu.v v8, v4
# CHECK-INST: vfcvt.f.xu.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x41,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x41,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 41 8a <unknown>
+# CHECK-UNKNOWN: 57 14 41 4a <unknown>
vfcvt.f.x.v v8, v4, v0.t
# CHECK-INST: vfcvt.f.x.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x41,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x41,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 41 88 <unknown>
+# CHECK-UNKNOWN: 57 94 41 48 <unknown>
vfcvt.f.x.v v8, v4
# CHECK-INST: vfcvt.f.x.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x41,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x41,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 41 8a <unknown>
+# CHECK-UNKNOWN: 57 94 41 4a <unknown>
+
+vfcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 43 48 <unknown>
+
+vfcvt.rtz.xu.f.v v8, v4
+# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 43 4a <unknown>
+
+vfcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 43 48 <unknown>
+
+vfcvt.rtz.x.f.v v8, v4
+# CHECK-INST: vfcvt.rtz.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 43 4a <unknown>
vfwcvt.xu.f.v v8, v4, v0.t
# CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x44,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x44,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 44 88 <unknown>
+# CHECK-UNKNOWN: 57 14 44 48 <unknown>
vfwcvt.xu.f.v v8, v4
# CHECK-INST: vfwcvt.xu.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x44,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x44,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 44 8a <unknown>
+# CHECK-UNKNOWN: 57 14 44 4a <unknown>
vfwcvt.x.f.v v8, v4, v0.t
# CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x44,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x44,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 44 88 <unknown>
+# CHECK-UNKNOWN: 57 94 44 48 <unknown>
vfwcvt.x.f.v v8, v4
# CHECK-INST: vfwcvt.x.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x44,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x44,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 44 8a <unknown>
+# CHECK-UNKNOWN: 57 94 44 4a <unknown>
vfwcvt.f.xu.v v8, v4, v0.t
# CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x45,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x45,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 45 88 <unknown>
+# CHECK-UNKNOWN: 57 14 45 48 <unknown>
vfwcvt.f.xu.v v8, v4
# CHECK-INST: vfwcvt.f.xu.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x45,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x45,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 45 8a <unknown>
+# CHECK-UNKNOWN: 57 14 45 4a <unknown>
vfwcvt.f.x.v v8, v4, v0.t
# CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x45,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x45,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 45 88 <unknown>
+# CHECK-UNKNOWN: 57 94 45 48 <unknown>
vfwcvt.f.x.v v8, v4
# CHECK-INST: vfwcvt.f.x.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x45,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x45,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 45 8a <unknown>
+# CHECK-UNKNOWN: 57 94 45 4a <unknown>
vfwcvt.f.f.v v8, v4, v0.t
# CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x46,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x46,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 46 88 <unknown>
+# CHECK-UNKNOWN: 57 14 46 48 <unknown>
vfwcvt.f.f.v v8, v4
# CHECK-INST: vfwcvt.f.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x46,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 4a <unknown>
+
+vfwcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x47,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 47 48 <unknown>
+
+vfwcvt.rtz.xu.f.v v8, v4
+# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x47,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 46 8a <unknown>
+# CHECK-UNKNOWN: 57 14 47 4a <unknown>
+
+vfwcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x47,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 47 48 <unknown>
+
+vfwcvt.rtz.x.f.v v8, v4
+# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x47,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 47 4a <unknown>
vfncvt.xu.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x48,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 88 <unknown>
+# CHECK-UNKNOWN: 57 14 48 48 <unknown>
vfncvt.xu.f.w v8, v4
# CHECK-INST: vfncvt.xu.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8a <unknown>
+# CHECK-UNKNOWN: 57 14 48 4a <unknown>
vfncvt.x.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.x.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x48,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x48,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 48 88 <unknown>
+# CHECK-UNKNOWN: 57 94 48 48 <unknown>
vfncvt.x.f.w v8, v4
# CHECK-INST: vfncvt.x.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x48,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x48,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 48 8a <unknown>
+# CHECK-UNKNOWN: 57 94 48 4a <unknown>
vfncvt.f.xu.w v8, v4, v0.t
# CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x49,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x49,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 49 88 <unknown>
+# CHECK-UNKNOWN: 57 14 49 48 <unknown>
vfncvt.f.xu.w v8, v4
# CHECK-INST: vfncvt.f.xu.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x49,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x49,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 49 8a <unknown>
+# CHECK-UNKNOWN: 57 14 49 4a <unknown>
vfncvt.f.x.w v8, v4, v0.t
# CHECK-INST: vfncvt.f.x.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x49,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x49,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 49 88 <unknown>
+# CHECK-UNKNOWN: 57 94 49 48 <unknown>
vfncvt.f.x.w v8, v4
# CHECK-INST: vfncvt.f.x.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x49,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x49,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 49 8a <unknown>
+# CHECK-UNKNOWN: 57 94 49 4a <unknown>
vfncvt.f.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.f.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x4a,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 4a 88 <unknown>
+# CHECK-UNKNOWN: 57 14 4a 48 <unknown>
vfncvt.f.f.w v8, v4
# CHECK-INST: vfncvt.f.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 4a 8a <unknown>
+# CHECK-UNKNOWN: 57 14 4a 4a <unknown>
vfncvt.rod.f.f.w v8, v4, v0.t
# CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x4a,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x48]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 4a 88 <unknown>
+# CHECK-UNKNOWN: 57 94 4a 48 <unknown>
vfncvt.rod.f.f.w v8, v4
# CHECK-INST: vfncvt.rod.f.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 4a <unknown>
+
+vfncvt.rtz.xu.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4b,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4b 48 <unknown>
+
+vfncvt.rtz.xu.f.w v8, v4
+# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x4b,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4b 4a <unknown>
+
+vfncvt.rtz.x.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rtz.x.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4b,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4b 48 <unknown>
+
+vfncvt.rtz.x.f.w v8, v4
+# CHECK-INST: vfncvt.rtz.x.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4b,0x4a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 4a 8a <unknown>
+# CHECK-UNKNOWN: 57 94 4b 4a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/ext.s b/llvm/test/MC/RISCV/rvv/ext.s
new file mode 100644
index 000000000000..45ac980b47b6
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/ext.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vzext.vf2 v8, v4, v0.t
+# CHECK-INST: vzext.vf2 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 43 48 <unknown>
+
+vzext.vf2 v8, v4
+# CHECK-INST: vzext.vf2 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 43 4a <unknown>
+
+vsext.vf2 v8, v4, v0.t
+# CHECK-INST: vsext.vf2 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 43 48 <unknown>
+
+vsext.vf2 v8, v4
+# CHECK-INST: vsext.vf2 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 43 4a <unknown>
+
+vzext.vf4 v8, v4, v0.t
+# CHECK-INST: vzext.vf4 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x42,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 48 <unknown>
+
+vzext.vf4 v8, v4
+# CHECK-INST: vzext.vf4 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x42,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 4a <unknown>
+
+vsext.vf4 v8, v4, v0.t
+# CHECK-INST: vsext.vf4 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x42,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 42 48 <unknown>
+
+vsext.vf4 v8, v4
+# CHECK-INST: vsext.vf4 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x42,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 42 4a <unknown>
+
+vzext.vf8 v8, v4, v0.t
+# CHECK-INST: vzext.vf8 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x41,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 48 <unknown>
+
+vzext.vf8 v8, v4
+# CHECK-INST: vzext.vf8 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x41,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 4a <unknown>
+
+vsext.vf8 v8, v4, v0.t
+# CHECK-INST: vsext.vf8 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 48 <unknown>
+
+vsext.vf8 v8, v4
+# CHECK-INST: vsext.vf8 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 4a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fcompare.s b/llvm/test/MC/RISCV/rvv/fcompare.s
index 9ad55dc54a07..4bb4e2d966f2 100644
--- a/llvm/test/MC/RISCV/rvv/fcompare.s
+++ b/llvm/test/MC/RISCV/rvv/fcompare.s
@@ -151,3 +151,9 @@ vmfge.vv v8, v20, v4
# CHECK-ENCODING: [0x57,0x14,0x4a,0x66]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 14 4a 66 <unknown>
+
+vmfeq.vv v0, v4, v20, v0.t
+# CHECK-INST: vmfeq.vv v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x10,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 10 4a 60 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s
index 768800def424..b9e03842fa2d 100644
--- a/llvm/test/MC/RISCV/rvv/fothers.s
+++ b/llvm/test/MC/RISCV/rvv/fothers.s
@@ -10,30 +10,54 @@
vfsqrt.v v8, v4, v0.t
# CHECK-INST: vfsqrt.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8c]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8c <unknown>
+# CHECK-UNKNOWN: 57 14 40 4c <unknown>
vfsqrt.v v8, v4
# CHECK-INST: vfsqrt.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8e]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8e <unknown>
+# CHECK-UNKNOWN: 57 14 40 4e <unknown>
vfclass.v v8, v4, v0.t
# CHECK-INST: vfclass.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8c]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8c <unknown>
+# CHECK-UNKNOWN: 57 14 48 4c <unknown>
vfclass.v v8, v4
# CHECK-INST: vfclass.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8e]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8e <unknown>
+# CHECK-UNKNOWN: 57 14 48 4e <unknown>
vfmerge.vfm v8, v4, fa0, v0
# CHECK-INST: vfmerge.vfm v8, v4, fa0, v0
# CHECK-ENCODING: [0x57,0x54,0x45,0x5c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 54 45 5c <unknown>
+
+vfslide1up.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfslide1up.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 38 <unknown>
+
+vfslide1up.vf v8, v4, fa0
+# CHECK-INST: vfslide1up.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3a <unknown>
+
+vfslide1down.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfslide1down.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3c <unknown>
+
+vfslide1down.vf v8, v4, fa0
+# CHECK-INST: vfslide1down.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s
index 2131dadff8ca..a85e676f9a8c 100644
--- a/llvm/test/MC/RISCV/rvv/freduction.s
+++ b/llvm/test/MC/RISCV/rvv/freduction.s
@@ -79,3 +79,9 @@ vfwredsum.vs v8, v4, v20
# CHECK-ENCODING: [0x57,0x14,0x4a,0xc6]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 14 4a c6 <unknown>
+
+vfredosum.vs v0, v4, v20, v0.t
+# CHECK-INST: vfredosum.vs v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x10,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 10 4a 0c <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index 814093eba505..615dc08ad67c 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -2,22 +2,34 @@
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
vsetvli a2, a0, e31
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e32,m3
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, m1,e32
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e32,m16
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e2048,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vsetvli a2, a0, e1,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,tx
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,ta,mx
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,ma
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,mu
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
vadd.vv v1, v3, v2, v4.t
# CHECK-ERROR: operand must be v0.t
@@ -47,10 +59,6 @@ vfwcvt.xu.f.v v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v2
-vfwcvt.xu.f.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v3
-
vfwcvt.x.f.v v0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwcvt.x.f.v v0, v2, v0.t
@@ -59,10 +67,6 @@ vfwcvt.x.f.v v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v2
-vfwcvt.x.f.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v3
-
vfwcvt.f.xu.v v0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v0, v2, v0.t
@@ -71,10 +75,6 @@ vfwcvt.f.xu.v v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v2
-vfwcvt.f.xu.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v3
-
vfwcvt.f.x.v v0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwcvt.f.x.v v0, v2, v0.t
@@ -83,10 +83,6 @@ vfwcvt.f.x.v v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v2
-vfwcvt.f.x.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v3
-
vfwcvt.f.f.v v0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwcvt.f.f.v v0, v2, v0.t
@@ -95,10 +91,6 @@ vfwcvt.f.f.v v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v2
-vfwcvt.f.f.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v3
-
vslideup.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vslideup.vx v0, v2, a0, v0.t
@@ -127,10 +119,6 @@ vnsrl.wv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4
-vnsrl.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsrl.wv v3, v2, v4
-
vnsrl.wx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0
@@ -143,10 +131,6 @@ vnsra.wv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4
-vnsra.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsra.wv v3, v2, v4
-
vnsra.wx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0
@@ -159,10 +143,6 @@ vnclipu.wv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4
-vnclipu.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclipu.wv v3, v2, v4
-
vnclipu.wx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0
@@ -175,10 +155,6 @@ vnclip.wv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4
-vnclip.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclip.wv v3, v2, v4
-
vnclip.wx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0
@@ -191,50 +167,26 @@ vfncvt.xu.f.w v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2
-vfncvt.xu.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.xu.f.w v3, v2
-
vfncvt.x.f.w v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2
-vfncvt.x.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.x.f.w v3, v2
-
vfncvt.f.xu.w v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2
-vfncvt.f.xu.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.xu.w v3, v2
-
vfncvt.f.x.w v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2
-vfncvt.f.x.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.x.w v3, v2
-
vfncvt.f.f.w v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2
-vfncvt.f.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.f.w v3, v2
-
vfncvt.rod.f.f.w v2, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2
-vfncvt.rod.f.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v3, v2
-
vrgather.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t
@@ -267,10 +219,6 @@ vwaddu.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwaddu.vv v2, v2, v4
-vwaddu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwaddu.vv v2, v3, v4
-
vwsubu.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwsubu.vv v0, v2, v4, v0.t
@@ -279,10 +227,6 @@ vwsubu.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwsubu.vv v2, v2, v4
-vwsubu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsubu.vv v2, v3, v4
-
vwadd.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwadd.vv v0, v2, v4, v0.t
@@ -291,10 +235,6 @@ vwadd.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwadd.vv v2, v2, v4
-vwadd.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwadd.vv v2, v3, v4
-
vwsub.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwsub.vv v0, v2, v4, v0.t
@@ -303,10 +243,6 @@ vwsub.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwsub.vv v2, v2, v4
-vwsub.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsub.vv v2, v3, v4
-
vwmul.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmul.vv v0, v2, v4, v0.t
@@ -315,10 +251,6 @@ vwmul.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmul.vv v2, v2, v4
-vwmul.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmul.vv v2, v3, v4
-
vwmulu.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmulu.vv v0, v2, v4, v0.t
@@ -327,10 +259,6 @@ vwmulu.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmulu.vv v2, v2, v4
-vwmulu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulu.vv v2, v3, v4
-
vwmulsu.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmulsu.vv v0, v2, v4, v0.t
@@ -339,10 +267,6 @@ vwmulsu.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmulsu.vv v2, v2, v4
-vwmulsu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulsu.vv v2, v3, v4
-
vwmaccu.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmaccu.vv v0, v4, v2, v0.t
@@ -351,10 +275,6 @@ vwmaccu.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v2
-vwmaccu.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v3
-
vwmacc.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmacc.vv v0, v4, v2, v0.t
@@ -363,10 +283,6 @@ vwmacc.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v2
-vwmacc.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v3
-
vwmaccsu.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmaccsu.vv v0, v4, v2, v0.t
@@ -375,10 +291,6 @@ vwmaccsu.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v2
-vwmaccsu.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v3
-
vfwadd.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwadd.vv v0, v2, v4, v0.t
@@ -387,10 +299,6 @@ vfwadd.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwadd.vv v2, v2, v4
-vfwadd.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwadd.vv v2, v3, v4
-
vfwsub.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwsub.vv v0, v2, v4, v0.t
@@ -399,10 +307,6 @@ vfwsub.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwsub.vv v2, v2, v4
-vfwsub.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwsub.vv v2, v3, v4
-
vfwmul.vv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwmul.vv v0, v2, v4, v0.t
@@ -411,10 +315,6 @@ vfwmul.vv v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwmul.vv v2, v2, v4
-vfwmul.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmul.vv v2, v3, v4
-
vfwmacc.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwmacc.vv v0, v4, v2, v0.t
@@ -423,10 +323,6 @@ vfwmacc.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v2
-vfwmacc.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v3
-
vfwnmacc.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwnmacc.vv v0, v4, v2, v0.t
@@ -435,10 +331,6 @@ vfwnmacc.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v2
-vfwnmacc.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v3
-
vfwmsac.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwmsac.vv v0, v4, v2, v0.t
@@ -447,10 +339,6 @@ vfwmsac.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v2
-vfwmsac.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v3
-
vfwnmsac.vv v0, v4, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwnmsac.vv v0, v4, v2, v0.t
@@ -459,10 +347,6 @@ vfwnmsac.vv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v2
-vfwnmsac.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v3
-
vwaddu.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwaddu.vx v0, v2, a0, v0.t
@@ -471,10 +355,6 @@ vwaddu.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwaddu.vx v2, v2, a0
-vwaddu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwaddu.vx v2, v3, a0
-
vwsubu.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwsubu.vx v0, v2, a0, v0.t
@@ -483,10 +363,6 @@ vwsubu.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwsubu.vx v2, v2, a0
-vwsubu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsubu.vx v2, v3, a0
-
vwadd.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwadd.vx v0, v2, a0, v0.t
@@ -495,10 +371,6 @@ vwadd.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwadd.vx v2, v2, a0
-vwadd.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwadd.vx v2, v3, a0
-
vwsub.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwsub.vx v0, v2, a0, v0.t
@@ -507,10 +379,6 @@ vwsub.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwsub.vx v2, v2, a0
-vwsub.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsub.vx v2, v3, a0
-
vwmul.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmul.vx v0, v2, a0, v0.t
@@ -519,10 +387,6 @@ vwmul.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmul.vx v2, v2, a0
-vwmul.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmul.vx v2, v3, a0
-
vwmulu.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmulu.vx v0, v2, a0, v0.t
@@ -531,10 +395,6 @@ vwmulu.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmulu.vx v2, v2, a0
-vwmulu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulu.vx v2, v3, a0
-
vwmulsu.vx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmulsu.vx v0, v2, a0, v0.t
@@ -543,10 +403,6 @@ vwmulsu.vx v2, v2, a0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmulsu.vx v2, v2, a0
-vwmulsu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulsu.vx v2, v3, a0
-
vwmaccu.vx v0, a0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmaccu.vx v0, a0, v2, v0.t
@@ -555,10 +411,6 @@ vwmaccu.vx v2, a0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v2
-vwmaccu.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v3
-
vwmacc.vx v0, a0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmacc.vx v0, a0, v2, v0.t
@@ -567,10 +419,6 @@ vwmacc.vx v2, a0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v2
-vwmacc.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v3
-
vwmaccsu.vx v0, a0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmaccsu.vx v0, a0, v2, v0.t
@@ -579,10 +427,6 @@ vwmaccsu.vx v2, a0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v2
-vwmaccsu.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v3
-
vwmaccus.vx v0, a0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwmaccus.vx v0, a0, v2, v0.t
@@ -591,10 +435,6 @@ vwmaccus.vx v2, a0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v2
-vwmaccus.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v3
-
vfwadd.vf v0, v2, fa0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwadd.vf v0, v2, fa0, v0.t
@@ -603,10 +443,6 @@ vfwadd.vf v2, v2, fa0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwadd.vf v2, v2, fa0
-vfwadd.vf v2, v3, fa0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwadd.vf v2, v3, fa0
-
vfwsub.vf v0, v2, fa0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwsub.vf v0, v2, fa0, v0.t
@@ -615,10 +451,6 @@ vfwsub.vf v2, v2, fa0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwsub.vf v2, v2, fa0
-vfwsub.vf v2, v3, fa0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwsub.vf v2, v3, fa0
-
vfwmul.vf v0, v2, fa0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwmul.vf v0, v2, fa0, v0.t
@@ -627,10 +459,6 @@ vfwmul.vf v2, v2, fa0
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwmul.vf v2, v2, fa0
-vfwmul.vf v2, v3, fa0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmul.vf v2, v3, fa0
-
vfwmacc.vf v0, fa0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwmacc.vf v0, fa0, v2, v0.t
@@ -639,10 +467,6 @@ vfwmacc.vf v2, fa0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v2
-vfwmacc.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v3
-
vfwnmacc.vf v0, fa0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwnmacc.vf v0, fa0, v2, v0.t
@@ -651,10 +475,6 @@ vfwnmacc.vf v2, fa0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v2
-vfwnmacc.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v3
-
vfwmsac.vf v0, fa0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwmsac.vf v0, fa0, v2, v0.t
@@ -663,10 +483,6 @@ vfwmsac.vf v2, fa0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v2
-vfwmsac.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v3
-
vfwnmsac.vf v0, fa0, v2, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwnmsac.vf v0, fa0, v2, v0.t
@@ -675,10 +491,6 @@ vfwnmsac.vf v2, fa0, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v2
-vfwnmsac.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v3
-
vcompress.vm v2, v2, v4
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vcompress.vm v2, v2, v4
@@ -691,10 +503,6 @@ vwaddu.wv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v2
-vwaddu.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v3
-
vwsubu.wv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwsubu.wv v0, v2, v4, v0.t
@@ -703,10 +511,6 @@ vwsubu.wv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v2
-vwsubu.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v3
-
vwadd.wv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwadd.wv v0, v2, v4, v0.t
@@ -715,10 +519,6 @@ vwadd.wv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v2
-vwadd.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v3
-
vwsub.wv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwsub.wv v0, v2, v4, v0.t
@@ -727,10 +527,6 @@ vwsub.wv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v2
-vwsub.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v3
-
vfwadd.wv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwadd.wv v0, v2, v4, v0.t
@@ -739,10 +535,6 @@ vfwadd.wv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v2
-vfwadd.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v3
-
vfwsub.wv v0, v2, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwsub.wv v0, v2, v4, v0.t
@@ -751,10 +543,6 @@ vfwsub.wv v2, v4, v2
# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v2
-vfwsub.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v3
-
vwaddu.wx v0, v2, a0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vwaddu.wx v0, v2, a0, v0.t
@@ -778,3 +566,27 @@ vfwadd.wf v0, v2, fa0, v0.t
vfwsub.wf v0, v2, fa0, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t
+
+vadc.vvm v0, v2, v4, v0
+# CHECK-ERROR: The destination vector register group cannot be V0.
+# CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0
+
+vmadc.vvm v2, v2, v4, v0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0
+
+vmadc.vvm v4, v2, v4, v0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0
+
+vadd.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t
+
+vadd.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vadd.vx v0, v2, a0, v0.t
+
+vadd.vi v0, v2, 1, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vadd.vi v0, v2, 1, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s
index c8284b561f4a..eac3191c2d6b 100644
--- a/llvm/test/MC/RISCV/rvv/load.s
+++ b/llvm/test/MC/RISCV/rvv/load.s
@@ -8,332 +8,392 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vlb.v v8, (a0), v0.t
-# CHECK-INST: vlb.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 10 <unknown>
-
-vlb.v v8, (a0)
-# CHECK-INST: vlb.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 12 <unknown>
-
-vlh.v v8, (a0), v0.t
-# CHECK-INST: vlh.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 10 <unknown>
-
-vlh.v v8, (a0)
-# CHECK-INST: vlh.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 12 <unknown>
-
-vlw.v v8, (a0), v0.t
-# CHECK-INST: vlw.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 10 <unknown>
-
-vlw.v v8, (a0)
-# CHECK-INST: vlw.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 12 <unknown>
-
-vlbu.v v8, (a0), v0.t
-# CHECK-INST: vlbu.v v8, (a0), v0.t
+vle8.v v8, (a0), v0.t
+# CHECK-INST: vle8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 00 <unknown>
-vlbu.v v8, (a0)
-# CHECK-INST: vlbu.v v8, (a0)
+vle8.v v8, (a0)
+# CHECK-INST: vle8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 02 <unknown>
-vlhu.v v8, (a0), v0.t
-# CHECK-INST: vlhu.v v8, (a0), v0.t
+vle16.v v8, (a0), v0.t
+# CHECK-INST: vle16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 00 <unknown>
-vlhu.v v8, (a0)
-# CHECK-INST: vlhu.v v8, (a0)
+vle16.v v8, (a0)
+# CHECK-INST: vle16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 02 <unknown>
-vlwu.v v8, (a0), v0.t
-# CHECK-INST: vlwu.v v8, (a0), v0.t
+vle32.v v8, (a0), v0.t
+# CHECK-INST: vle32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 00 <unknown>
-vlwu.v v8, (a0)
-# CHECK-INST: vlwu.v v8, (a0)
+vle32.v v8, (a0)
+# CHECK-INST: vle32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 02 <unknown>
-vlbff.v v8, (a0), v0.t
-# CHECK-INST: vlbff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
+vle64.v v8, (a0), v0.t
+# CHECK-INST: vle64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 11 <unknown>
+# CHECK-UNKNOWN: 07 74 05 00 <unknown>
-vlbff.v v8, (a0)
-# CHECK-INST: vlbff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
+vle64.v v8, (a0)
+# CHECK-INST: vle64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 13 <unknown>
+# CHECK-UNKNOWN: 07 74 05 02 <unknown>
-vlhff.v v8, (a0), v0.t
-# CHECK-INST: vlhff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
+vle128.v v8, (a0), v0.t
+# CHECK-INST: vle128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 11 <unknown>
+# CHECK-UNKNOWN: 07 04 05 10 <unknown>
-vlhff.v v8, (a0)
-# CHECK-INST: vlhff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
+vle128.v v8, (a0)
+# CHECK-INST: vle128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 13 <unknown>
+# CHECK-UNKNOWN: 07 04 05 12 <unknown>
-vlwff.v v8, (a0), v0.t
-# CHECK-INST: vlwff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
+vle256.v v8, (a0), v0.t
+# CHECK-INST: vle256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 11 <unknown>
+# CHECK-UNKNOWN: 07 54 05 10 <unknown>
-vlwff.v v8, (a0)
-# CHECK-INST: vlwff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
+vle256.v v8, (a0)
+# CHECK-INST: vle256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+# CHECK-UNKNOWN: 07 54 05 12 <unknown>
-vlbuff.v v8, (a0), v0.t
-# CHECK-INST: vlbuff.v v8, (a0), v0.t
+vle512.v v8, (a0), v0.t
+# CHECK-INST: vle512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 10 <unknown>
+
+vle512.v v8, (a0)
+# CHECK-INST: vle512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 12 <unknown>
+
+vle1024.v v8, (a0), v0.t
+# CHECK-INST: vle1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 10 <unknown>
+
+vle1024.v v8, (a0)
+# CHECK-INST: vle1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 12 <unknown>
+
+vle8ff.v v8, (a0), v0.t
+# CHECK-INST: vle8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 01 <unknown>
-vlbuff.v v8, (a0)
-# CHECK-INST: vlbuff.v v8, (a0)
+vle8ff.v v8, (a0)
+# CHECK-INST: vle8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 05 03 <unknown>
-vlhuff.v v8, (a0), v0.t
-# CHECK-INST: vlhuff.v v8, (a0), v0.t
+vle16ff.v v8, (a0), v0.t
+# CHECK-INST: vle16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 01 <unknown>
-vlhuff.v v8, (a0)
-# CHECK-INST: vlhuff.v v8, (a0)
+vle16ff.v v8, (a0)
+# CHECK-INST: vle16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 05 03 <unknown>
-vlwuff.v v8, (a0), v0.t
-# CHECK-INST: vlwuff.v v8, (a0), v0.t
+vle32ff.v v8, (a0), v0.t
+# CHECK-INST: vle32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 01 <unknown>
-vlwuff.v v8, (a0)
-# CHECK-INST: vlwuff.v v8, (a0)
+vle32ff.v v8, (a0)
+# CHECK-INST: vle32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 05 03 <unknown>
-vleff.v v8, (a0), v0.t
-# CHECK-INST: vleff.v v8, (a0), v0.t
+vle64ff.v v8, (a0), v0.t
+# CHECK-INST: vle64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 05 01 <unknown>
-vleff.v v8, (a0)
-# CHECK-INST: vleff.v v8, (a0)
+vle64ff.v v8, (a0)
+# CHECK-INST: vle64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x03]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 05 03 <unknown>
-vlsb.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsb.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
+vle128ff.v v8, (a0), v0.t
+# CHECK-INST: vle128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 04 05 11 <unknown>
-vlsb.v v8, (a0), a1
-# CHECK-INST: vlsb.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
+vle128ff.v v8, (a0)
+# CHECK-INST: vle128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 04 05 13 <unknown>
-vlsh.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsh.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
+vle256ff.v v8, (a0), v0.t
+# CHECK-INST: vle256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 54 05 11 <unknown>
-vlsh.v v8, (a0), a1
-# CHECK-INST: vlsh.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
+vle256ff.v v8, (a0)
+# CHECK-INST: vle256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 54 05 13 <unknown>
-vlsw.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsw.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
+vle512ff.v v8, (a0), v0.t
+# CHECK-INST: vle512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 64 05 11 <unknown>
-vlsw.v v8, (a0), a1
-# CHECK-INST: vlsw.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
+vle512ff.v v8, (a0)
+# CHECK-INST: vle512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+
+vle1024ff.v v8, (a0), v0.t
+# CHECK-INST: vle1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 11 <unknown>
+
+vle1024ff.v v8, (a0)
+# CHECK-INST: vle1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 13 <unknown>
-vlsbu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t
+vlse8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 b5 08 <unknown>
-vlsbu.v v8, (a0), a1
-# CHECK-INST: vlsbu.v v8, (a0), a1
+vlse8.v v8, (a0), a1
+# CHECK-INST: vlse8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 b5 0a <unknown>
-vlshu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlshu.v v8, (a0), a1, v0.t
+vlse16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 b5 08 <unknown>
-vlshu.v v8, (a0), a1
-# CHECK-INST: vlshu.v v8, (a0), a1
+vlse16.v v8, (a0), a1
+# CHECK-INST: vlse16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 b5 0a <unknown>
-vlswu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlswu.v v8, (a0), a1, v0.t
+vlse32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 b5 08 <unknown>
-vlswu.v v8, (a0), a1
-# CHECK-INST: vlswu.v v8, (a0), a1
+vlse32.v v8, (a0), a1
+# CHECK-INST: vlse32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 b5 0a <unknown>
-vlse.v v8, (a0), a1, v0.t
-# CHECK-INST: vlse.v v8, (a0), a1, v0.t
+vlse64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 b5 08 <unknown>
-vlse.v v8, (a0), a1
-# CHECK-INST: vlse.v v8, (a0), a1
+vlse64.v v8, (a0), a1
+# CHECK-INST: vlse64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 b5 0a <unknown>
-vlxb.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxb.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+vlse128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
-vlxb.v v8, (a0), v4
-# CHECK-INST: vlxb.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+vlse128.v v8, (a0), a1
+# CHECK-INST: vlse128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
-vlxh.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxh.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+vlse256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
-vlxh.v v8, (a0), v4
-# CHECK-INST: vlxh.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+vlse256.v v8, (a0), a1
+# CHECK-INST: vlse256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
-vlxw.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxw.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+vlse512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
-vlxw.v v8, (a0), v4
-# CHECK-INST: vlxw.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+vlse512.v v8, (a0), a1
+# CHECK-INST: vlse512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+
+vlse1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 18 <unknown>
-vlxbu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t
+vlse1024.v v8, (a0), a1
+# CHECK-INST: vlse1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 1a <unknown>
+
+vlxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 45 0c <unknown>
-vlxbu.v v8, (a0), v4
-# CHECK-INST: vlxbu.v v8, (a0), v4
+vlxei8.v v8, (a0), v4
+# CHECK-INST: vlxei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 45 0e <unknown>
-vlxhu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t
+vlxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 45 0c <unknown>
-vlxhu.v v8, (a0), v4
-# CHECK-INST: vlxhu.v v8, (a0), v4
+vlxei16.v v8, (a0), v4
+# CHECK-INST: vlxei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 54 45 0e <unknown>
-vlxwu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t
+vlxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 45 0c <unknown>
-vlxwu.v v8, (a0), v4
-# CHECK-INST: vlxwu.v v8, (a0), v4
+vlxei32.v v8, (a0), v4
+# CHECK-INST: vlxei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 64 45 0e <unknown>
-vlxe.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxe.v v8, (a0), v4, v0.t
+vlxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 45 0c <unknown>
-vlxe.v v8, (a0), v4
-# CHECK-INST: vlxe.v v8, (a0), v4
+vlxei64.v v8, (a0), v4
+# CHECK-INST: vlxei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 74 45 0e <unknown>
+vlxei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+
+vlxei128.v v8, (a0), v4
+# CHECK-INST: vlxei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+
+vlxei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+
+vlxei256.v v8, (a0), v4
+# CHECK-INST: vlxei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+
+vlxei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+
+vlxei512.v v8, (a0), v4
+# CHECK-INST: vlxei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+
+vlxei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 1c <unknown>
+
+vlxei1024.v v8, (a0), v4
+# CHECK-INST: vlxei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 1e <unknown>
+
vl1r.v v8, (a0)
# CHECK-INST: vl1r.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x85,0x02]
+# CHECK-ENCODING: [0x07,0x04,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 85 02 <unknown>
+# CHECK-UNKNOWN: 07 04 85 02 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/mask.s b/llvm/test/MC/RISCV/rvv/mask.s
index d2157bc215bf..ef029388da9c 100644
--- a/llvm/test/MC/RISCV/rvv/mask.s
+++ b/llvm/test/MC/RISCV/rvv/mask.s
@@ -140,8 +140,8 @@ vid.v v8
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 a4 08 52 <unknown>
-vmcpy.m v8, v4
-# CHECK-INST: vmcpy.m v8, v4
+vmmv.m v8, v4
+# CHECK-INST: vmmv.m v8, v4
# CHECK-ENCODING: [0x57,0x24,0x42,0x66]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 24 42 66 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/reduction.s b/llvm/test/MC/RISCV/rvv/reduction.s
index dc5adec0a566..7599c603363f 100644
--- a/llvm/test/MC/RISCV/rvv/reduction.s
+++ b/llvm/test/MC/RISCV/rvv/reduction.s
@@ -127,3 +127,9 @@ vwredsum.vs v8, v4, v20
# CHECK-ENCODING: [0x57,0x04,0x4a,0xc6]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 04 4a c6 <unknown>
+
+vredsum.vs v0, v4, v20, v0.t
+# CHECK-INST: vredsum.vs v0, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x20,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 20 4a 00 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s
index fd38631c4ba7..94f6556ea10c 100644
--- a/llvm/test/MC/RISCV/rvv/snippet.s
+++ b/llvm/test/MC/RISCV/rvv/snippet.s
@@ -5,28 +5,28 @@
# RUN: | FileCheck %s --check-prefix=CHECK-INST
loop:
- vsetvli a3, a0, e16,m4 # vtype = 16-bit integer vectors
-# CHECK-INST: d7 76 65 00 vsetvli a3, a0, e16,m4
- vlh.v v4, (a1) # Get 16b vector
-# CHECK-INST: 07 d2 05 12 vlh.v v4, (a1)
- slli t1, a3, 1 # Multiply length by two bytes/element
+ vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors
+# CHECK-INST: d7 76 65 0c vsetvli a3, a0, e16,m4,ta,ma
+ vle16.v v4, (a1) # Get 16b vector
+# CHECK-INST: 07 d2 05 02 vle16.v v4, (a1)
+ slli t1, a3, 1 # Multiply length by two bytes/element
# CHECK-INST: 13 93 16 00 slli t1, a3, 1
- add a1, a1, t1 # Bump pointer
+ add a1, a1, t1 # Bump pointer
# CHECK-INST: b3 85 65 00 add a1, a1, t1
- vwmul.vx v8, v4, x10 # 32b in <v8--v15>
+ vwmul.vx v8, v4, x10 # 32b in <v8--v15>
# CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0
- vsetvli x0, a0, e32,m8 # Operate on 32b values
-# CHECK-INST: 57 70 b5 00 vsetvli zero, a0, e32,m8
+ vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values
+# CHECK-INST: 57 70 b5 0c vsetvli zero, a0, e32,m8,ta,ma
vsrl.vi v8, v8, 3
# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3
- vsw.v v8, (a2) # Store vector of 32b
-# CHECK-INST: 27 64 06 02 vsw.v v8, (a2)
- slli t1, a3, 2 # Multiply length by four bytes/element
+ vse32.v v8, (a2) # Store vector of 32b
+# CHECK-INST: 27 64 06 02 vse32.v v8, (a2)
+ slli t1, a3, 2 # Multiply length by four bytes/element
# CHECK-INST: 13 93 26 00 slli t1, a3, 2
- add a2, a2, t1 # Bump pointer
+ add a2, a2, t1 # Bump pointer
# CHECK-INST: 33 06 66 00 add a2, a2, t1
- sub a0, a0, a3 # Decrement count
+ sub a0, a0, a3 # Decrement count
# CHECK-INST: 33 05 d5 40 sub a0, a0, a3
- bnez a0, loop # Any more?
+ bnez a0, loop # Any more?
# CHECK-INST: e3 1a 05 fc bnez a0, -44
diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s
index 9d25b593ef82..75dacb9d19e5 100644
--- a/llvm/test/MC/RISCV/rvv/store.s
+++ b/llvm/test/MC/RISCV/rvv/store.s
@@ -8,200 +8,296 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 05 00 <unknown>
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 05 02 <unknown>
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 05 00 <unknown>
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 05 02 <unknown>
-vsw.v v24, (a0), v0.t
-# CHECK-INST: vsw.v v24, (a0), v0.t
+vse32.v v24, (a0), v0.t
+# CHECK-INST: vse32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 05 00 <unknown>
-vsw.v v24, (a0)
-# CHECK-INST: vsw.v v24, (a0)
+vse32.v v24, (a0)
+# CHECK-INST: vse32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 05 02 <unknown>
-vse.v v24, (a0), v0.t
-# CHECK-INST: vse.v v24, (a0), v0.t
+vse64.v v24, (a0), v0.t
+# CHECK-INST: vse64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0x00]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 05 00 <unknown>
-vse.v v24, (a0)
-# CHECK-INST: vse.v v24, (a0)
+vse64.v v24, (a0)
+# CHECK-INST: vse64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 05 02 <unknown>
-vssb.v v24, (a0), a1, v0.t
-# CHECK-INST: vssb.v v24, (a0), a1, v0.t
+vse128.v v24, (a0), v0.t
+# CHECK-INST: vse128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 10 <unknown>
+
+vse128.v v24, (a0)
+# CHECK-INST: vse128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 12 <unknown>
+
+vse256.v v24, (a0), v0.t
+# CHECK-INST: vse256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 10 <unknown>
+
+vse256.v v24, (a0)
+# CHECK-INST: vse256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 12 <unknown>
+
+vse512.v v24, (a0), v0.t
+# CHECK-INST: vse512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 10 <unknown>
+
+vse512.v v24, (a0)
+# CHECK-INST: vse512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 12 <unknown>
+
+vse1024.v v24, (a0), v0.t
+# CHECK-INST: vse1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 10 <unknown>
+
+vse1024.v v24, (a0)
+# CHECK-INST: vse1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 12 <unknown>
+
+vsse8.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c b5 08 <unknown>
-vssb.v v24, (a0), a1
-# CHECK-INST: vssb.v v24, (a0), a1
+vsse8.v v24, (a0), a1
+# CHECK-INST: vsse8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c b5 0a <unknown>
-vssh.v v24, (a0), a1, v0.t
-# CHECK-INST: vssh.v v24, (a0), a1, v0.t
+vsse16.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c b5 08 <unknown>
-vssh.v v24, (a0), a1
-# CHECK-INST: vssh.v v24, (a0), a1
+vsse16.v v24, (a0), a1
+# CHECK-INST: vsse16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c b5 0a <unknown>
-vssw.v v24, (a0), a1, v0.t
-# CHECK-INST: vssw.v v24, (a0), a1, v0.t
+vsse32.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c b5 08 <unknown>
-vssw.v v24, (a0), a1
-# CHECK-INST: vssw.v v24, (a0), a1
+vsse32.v v24, (a0), a1
+# CHECK-INST: vsse32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c b5 0a <unknown>
-vsse.v v24, (a0), a1, v0.t
-# CHECK-INST: vsse.v v24, (a0), a1, v0.t
+vsse64.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x08]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c b5 08 <unknown>
-vsse.v v24, (a0), a1
-# CHECK-INST: vsse.v v24, (a0), a1
+vsse64.v v24, (a0), a1
+# CHECK-INST: vsse64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c b5 0a <unknown>
-vsxb.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxb.v v24, (a0), v4, v0.t
+vsse128.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 18 <unknown>
+
+vsse128.v v24, (a0), a1
+# CHECK-INST: vsse128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 1a <unknown>
+
+vsse256.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 18 <unknown>
+
+vsse256.v v24, (a0), a1
+# CHECK-INST: vsse256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 1a <unknown>
+
+vsse512.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 18 <unknown>
+
+vsse512.v v24, (a0), a1
+# CHECK-INST: vsse512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 1a <unknown>
+
+vsse1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 18 <unknown>
+
+vsse1024.v v24, (a0), a1
+# CHECK-INST: vsse1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 1a <unknown>
+
+vsxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 0c <unknown>
-vsxb.v v24, (a0), v4
-# CHECK-INST: vsxb.v v24, (a0), v4
+vsxei8.v v24, (a0), v4
+# CHECK-INST: vsxei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 0e <unknown>
-vsxh.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxh.v v24, (a0), v4, v0.t
+vsxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 0c <unknown>
-vsxh.v v24, (a0), v4
-# CHECK-INST: vsxh.v v24, (a0), v4
+vsxei16.v v24, (a0), v4
+# CHECK-INST: vsxei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 0e <unknown>
-vsxw.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxw.v v24, (a0), v4, v0.t
+vsxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 0c <unknown>
-vsxw.v v24, (a0), v4
-# CHECK-INST: vsxw.v v24, (a0), v4
+vsxei32.v v24, (a0), v4
+# CHECK-INST: vsxei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 0e <unknown>
-vsxe.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxe.v v24, (a0), v4, v0.t
+vsxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 0c <unknown>
-vsxe.v v24, (a0), v4
-# CHECK-INST: vsxe.v v24, (a0), v4
+vsxei64.v v24, (a0), v4
+# CHECK-INST: vsxei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 0e <unknown>
-vsuxb.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxb.v v24, (a0), v4, v0.t
+vsxei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei128.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 1c <unknown>
-vsuxb.v v24, (a0), v4
-# CHECK-INST: vsuxb.v v24, (a0), v4
+vsxei128.v v24, (a0), v4
+# CHECK-INST: vsxei128.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c 45 1e <unknown>
-vsuxh.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxh.v v24, (a0), v4, v0.t
+vsxei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei256.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 1c <unknown>
-vsuxh.v v24, (a0), v4
-# CHECK-INST: vsuxh.v v24, (a0), v4
+vsxei256.v v24, (a0), v4
+# CHECK-INST: vsxei256.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 5c 45 1e <unknown>
-vsuxw.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxw.v v24, (a0), v4, v0.t
+vsxei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei512.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 1c <unknown>
-vsuxw.v v24, (a0), v4
-# CHECK-INST: vsuxw.v v24, (a0), v4
+vsxei512.v v24, (a0), v4
+# CHECK-INST: vsxei512.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 6c 45 1e <unknown>
-vsuxe.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxe.v v24, (a0), v4, v0.t
+vsxei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei1024.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x1c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 1c <unknown>
-vsuxe.v v24, (a0), v4
-# CHECK-INST: vsuxe.v v24, (a0), v4
+vsxei1024.v v24, (a0), v4
+# CHECK-INST: vsxei1024.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x1e]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 7c 45 1e <unknown>
vs1r.v v24, (a0)
# CHECK-INST: vs1r.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x85,0x02]
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 85 02 <unknown>
+# CHECK-UNKNOWN: 27 0c 85 02 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s
index 784533445f0c..351d3febdf03 100644
--- a/llvm/test/MC/RISCV/rvv/vsetvl.s
+++ b/llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,11 +8,71 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vsetvli a2, a0, e32,m4
-# CHECK-INST: vsetvli a2, a0, e32,m4
-# CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 a5 00 <unknown>
+# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+
+vsetvli a2, a0, e32,m2,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x95,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 0c <unknown>
+
+vsetvli a2, a0, e32,m4,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 0c <unknown>
+
+vsetvli a2, a0, e32,m8,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 0c <unknown>
+
+vsetvli a2, a0, e32,mf2,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 0e <unknown>
+
+vsetvli a2, a0, e32,mf4,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 0e <unknown>
+
+vsetvli a2, a0, e32,mf8,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x95,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 0e <unknown>
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 <unknown>
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 <unknown>
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
vsetvl a2, a0, a1
# CHECK-INST: vsetvl a2, a0, a1
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