[llvm] 93fd8db - [PowerPC] Add Vector String Isolate instruction definitions and MC Tests
Amy Kwan via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 31 10:32:49 PDT 2020
Author: Albion Fung
Date: 2020-07-31T12:32:29-05:00
New Revision: 93fd8dbdc250330b84eeca3387e895407663d750
URL: https://github.com/llvm/llvm-project/commit/93fd8dbdc250330b84eeca3387e895407663d750
DIFF: https://github.com/llvm/llvm-project/commit/93fd8dbdc250330b84eeca3387e895407663d750.diff
LOG: [PowerPC] Add Vector String Isolate instruction definitions and MC Tests
This patch implements the instruction definition and MC tests for the vector
string isolate instructions.
Differential Revision: https://reviews.llvm.org/D84197
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 8ff0d460f47f..a92168789bbe 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -59,6 +59,39 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
string BaseName = "";
}
+// VX-Form: [ PO VT R VB RC XO ]
+class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OOL, IOL, asmstr, itin> {
+ bits<5> VT;
+ bits<5> VB;
+ bit RC = 0;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VT;
+ let Inst{11-15} = R;
+ let Inst{16-20} = VB;
+ let Inst{21} = RC;
+ let Inst{22-31} = xo;
+}
+
+// Multiclass definition to account for record and non-record form
+// instructions of VXRForm.
+multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
+ string asmbase, string asmstr,
+ InstrItinClass itin, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ itin, pattern>, RecFormRel;
+ let Defs = [CR6] in
+ def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ itin, []>, isRecordForm, RecFormRel;
+ }
+}
+
class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: PI<1, opcode, OOL, IOL, asmstr, itin> {
@@ -822,6 +855,14 @@ let Predicates = [IsISA3_1] in {
(int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB,
i32:$SH))]>;
+ defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB),
+ "vstribr", "$vT, $vB", IIC_VecGeneral, []>;
+ defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB),
+ "vstribl", "$vT, $vB", IIC_VecGeneral, []>;
+ defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB),
+ "vstrihr", "$vT, $vB", IIC_VecGeneral, []>;
+ defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB),
+ "vstrihl", "$vT, $vB", IIC_VecGeneral, []>;
def VINSW :
VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
"vinsw $vD, $rB, $UIM", IIC_VecGeneral,
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
index c8dae6a160a5..569068ab21a7 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -459,3 +459,26 @@
# CHECK: xscvsqqp 8, 28
0xfd 0xb 0xe6 0x88
+# CHECK: vstribr 2, 2
+0x10 0x41 0x10 0x0d
+
+# CHECK: vstribl 2, 2
+0x10 0x40 0x10 0x0d
+
+# CHECK: vstrihr 2, 2
+0x10 0x43 0x10 0x0d
+
+# CHECK: vstrihl 2, 2
+0x10 0x42 0x10 0x0d
+
+# CHECK: vstribr. 2, 2
+0x10 0x41 0x14 0x0d
+
+# CHECK: vstribl. 2, 2
+0x10 0x40 0x14 0x0d
+
+# CHECK: vstrihr. 2, 2
+0x10 0x43 0x14 0x0d
+
+# CHECK: vstrihl. 2, 2
+0x10 0x42 0x14 0x0d
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index bd1187f18ed8..6968821a3c09 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -585,3 +585,24 @@
# CHECK-BE: xscvsqqp 8, 28 # encoding: [0xfd,0x0b,0xe6,0x88]
# CHECK-LE: xscvsqqp 8, 28 # encoding: [0x88,0xe6,0x0b,0xfd]
xscvsqqp 8, 28
+# CHECK-BE: vstribr 2, 2 # encoding: [0x10,0x41,0x10,0x0d]
+# CHECK-LE: vstribr 2, 2 # encoding: [0x0d,0x10,0x41,0x10]
+ vstribr 2, 2
+# CHECK-BE: vstribl 2, 2 # encoding: [0x10,0x40,0x10,0x0d]
+# CHECK-LE: vstribl 2, 2 # encoding: [0x0d,0x10,0x40,0x10]
+ vstribl 2, 2
+# CHECK-BE: vstrihr 2, 2 # encoding: [0x10,0x43,0x10,0x0d]
+# CHECK-LE: vstrihr 2, 2 # encoding: [0x0d,0x10,0x43,0x10]
+ vstrihr 2, 2
+# CHECK-BE: vstribr. 2, 2 # encoding: [0x10,0x41,0x14,0x0d]
+# CHECK-LE: vstribr. 2, 2 # encoding: [0x0d,0x14,0x41,0x10]
+ vstribr. 2, 2
+# CHECK-BE: vstribl. 2, 2 # encoding: [0x10,0x40,0x14,0x0d]
+# CHECK-LE: vstribl. 2, 2 # encoding: [0x0d,0x14,0x40,0x10]
+ vstribl. 2, 2
+# CHECK-BE: vstrihr. 2, 2 # encoding: [0x10,0x43,0x14,0x0d]
+# CHECK-LE: vstrihr. 2, 2 # encoding: [0x0d,0x14,0x43,0x10]
+ vstrihr. 2, 2
+# CHECK-BE: vstrihl. 2, 2 # encoding: [0x10,0x42,0x14,0x0d]
+# CHECK-LE: vstrihl. 2, 2 # encoding: [0x0d,0x14,0x42,0x10]
+ vstrihl. 2, 2
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