[llvm] 7b11444 - Align store conditional address

[Krzysztof Parzyszek via llvm-commits]

Author: Brendon Cahoon
Date: 2020-07-30T10:42:00-05:00
New Revision: 7b114446c320de542c50c4c02f566e5d18adee33

URL: https://github.com/llvm/llvm-project/commit/7b114446c320de542c50c4c02f566e5d18adee33
DIFF: https://github.com/llvm/llvm-project/commit/7b114446c320de542c50c4c02f566e5d18adee33.diff

LOG: Align store conditional address

In cases where the alignment of the datatype is smaller than
expected by the instruction, the address is aligned. The aligned
address is used for the load, but wasn't used for the store
conditional, which resulted in a run-time alignment exception.

Added: 
    llvm/test/CodeGen/Hexagon/atomic-store-byte.ll

Modified: 
    llvm/lib/CodeGen/AtomicExpandPass.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp
index a5030305435c..c61531c5141a 100644
--- a/llvm/lib/CodeGen/AtomicExpandPass.cpp
+++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp
@@ -1239,7 +1239,8 @@ bool AtomicExpand::expandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
   Value *NewValueInsert =
       insertMaskedValue(Builder, LoadedTryStore, CI->getNewValOperand(), PMV);
   Value *StoreSuccess =
-      TLI->emitStoreConditional(Builder, NewValueInsert, Addr, MemOpOrder);
+      TLI->emitStoreConditional(Builder, NewValueInsert, PMV.AlignedAddr,
+                                MemOpOrder);
   StoreSuccess = Builder.CreateICmpEQ(
       StoreSuccess, ConstantInt::get(Type::getInt32Ty(Ctx), 0), "success");
   BasicBlock *RetryBB = HasReleasedLoadBB ? ReleasedLoadBB : StartBB;

diff  --git a/llvm/test/CodeGen/Hexagon/atomic-store-byte.ll b/llvm/test/CodeGen/Hexagon/atomic-store-byte.ll
new file mode 100644
index 000000000000..e3febe0264ad
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/atomic-store-byte.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=hexagon < %s | FileCheck %s
+
+; Test that the address for a store conditional for a byte is aligned
+; correctly to use the memw_locked instruction.
+
+; CHECK: [[REG:(r[0-9]+)]] = and(r{{[0-9]+}},#-4)
+; CHECK: = memw_locked([[REG]])
+; CHECK: memw_locked([[REG]],p{{[0-4]}}) =
+
+ at foo.a00 = internal global i8 0, align 1
+
+; Function Attrs: nofree norecurse nounwind
+define dso_local void @foo() local_unnamed_addr #0 {
+entry:
+  %0 = cmpxchg volatile i8* @foo.a00, i8 0, i8 1 seq_cst seq_cst
+  ret void
+}
+