[PATCH] D84899: [AMDGPU] Do not use undef on indirect source

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D84899#2183526 <https://reviews.llvm.org/D84899#2183526>, @arsenm wrote:

> In D84899#2183524 <https://reviews.llvm.org/D84899#2183524>, @rampitec wrote:
>
>> In D84899#2183507 <https://reviews.llvm.org/D84899#2183507>, @arsenm wrote:
>>
>>> In D84899#2183494 <https://reviews.llvm.org/D84899#2183494>, @rampitec wrote:
>>>
>>>> In D84899#2183476 <https://reviews.llvm.org/D84899#2183476>, @arsenm wrote:
>>>>
>>>>> I think I ran into these problems before. Last time I think I concluded we need to use pseudoinstructions and expand them after register allocation. I think the GPR index mode should definitely be using a pseudo instead of checking for the m0 implicit use.
>>>>
>>>> That's probably orthogonal. We can switch to pseudos, but we shall not fold immediate into an indirect move anyway, just in case it would be somehow produced. If you do not mind I would like to land this before any big changes as there is a blocker associated with the problem. Meanwhile I have started PSDB to see if it has not broke anything.
>>>
>>> This isn't the first time this technique has broken.
>>>
>>> This still needs to change GlobalISel to match
>>
>> Sure, I will add global isel part. Meanwhile do you remember why that undef was even set there?
>
> It doesn't actually read the content of that register. I think there was an associated liveness verifier error

Hm... My understanding that it may read that register. Not necessarily will but may. Anyway, I hope PSDB will show problems if there are any.


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