[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Luís Marques via Phabricator via llvm-commits]

luismarques added a comment.

In D84833#2184824 <https://reviews.llvm.org/D84833#2184824>, @jrtc27 wrote:

> I _believe_ we need:
>
>   isBranch = 1, isTerminator = 1, isBarrier = 1
>
> ?

Sounds about right. (I don't know offhand in what circumstances you have different values for `isTerminator` and `isBarrier`).
With that change we now run into an `llvm_unreachable` in `RISCVInstrInfo::isBranchOffsetInRange`, maybe it's just implementing that missing case.


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  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833