[PATCH] D84930: [AArch64] Consider instruction-level contract FMFs in combiner patterns.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: dmgreen, Gerolf, t.p.northover, samparker.
Herald added subscribers: danielkiss, steven.zhang, hiraditya, kristof.beyls.
Herald added a project: LLVM.
fhahn requested review of this revision.

Currently, instruction level fast math flags are not considered when
generating patterns for the machine combiner.

This currently leads to some missed opportunities to generate FMAs in
combination with `#pragma clang fp contract (fast)`.

For example, when building the example below with -O3 for AArch64, no
FMADD is generated. If built with -O2 and the DAGCombiner is used
instead of the MachineCombiner for FMAs, an FMADD is generated.

With this patch, the same code is generated in both cases.

  float madd_contract(float a, float b, float c) {
  #pragma clang fp contract (fast)
    return (a * b) + c;
  }


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84930

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/machine-combiner-instr-fmf.mir

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