[llvm] 9731ef3 - AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-07-28T16:49:55-04:00
New Revision: 9731ef3ec578a20be3d81d0ef340faf61bf797d4

URL: https://github.com/llvm/llvm-project/commit/9731ef3ec578a20be3d81d0ef340faf61bf797d4
DIFF: https://github.com/llvm/llvm-project/commit/9731ef3ec578a20be3d81d0ef340faf61bf797d4.diff

LOG: AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
index 9f6ebd00cd97..6c70b53b23c1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 def SGPRRegBank : RegisterBank<"SGPR",
-  [SReg_LO16, SReg_32, SReg_64, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
+  [SReg_LO16, SReg_32, SReg_64, SReg_96, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
 >;
 
 def VGPRRegBank : RegisterBank<"VGPR",