[PATCH] D84796: [LV] Add abs/smin/smax/umin/umax intrinsics to isTriviallyVectorizable

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/Transforms/LoopVectorize/intrinsic.ll:1250
+;CHECK-LABEL: @abs_i64(
+;CHECK: llvm.abs.v4i64
+;CHECK: ret void
----------------
Probably should check the immediate operand value


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  https://reviews.llvm.org/D84796/new/

https://reviews.llvm.org/D84796