[PATCH] D83730: [AMDGPU] Spill CSR VGPR which is reserved for SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM with nit. I really need to get back to the register allocation split patches



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Comment at: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp:249
   ArrayRef<MCPhysReg> AllVGPR32s = ST.getRegisterInfo()->getAllVGPR32(MF);
+
   for (MCPhysReg Reg : AllVGPR32s) {
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Extra whitespace change


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D83730/new/

https://reviews.llvm.org/D83730