[llvm] c3b8bd1 - [InstCombine] Always try to invert non-canonical predicate of an icmp
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 27 12:01:12 PDT 2020
FWIW Eigen's benchmarks are located here:
https://gitlab.com/libeigen/eigen/-/tree/master/bench
BM_MatrixVectorMultiply_Real_EigenColMajorFixed_float_13x16_
BM_MatrixVectorMultiply_Real_VectorOfEigenRowsDynamic_float_16x16_
BM_MatrixVectorMultiply_Real_VectorOfEigenRowsDynamic_float_13x16_
are the 3 that noticed the largest regressions after this.
On Sun, Jul 26, 2020 at 11:31 PM Eric Christopher <echristo at gmail.com>
wrote:
>
>
> On Fri, Jul 24, 2020 at 3:50 AM Roman Lebedev <lebedev.ri at gmail.com>
> wrote:
>
>> On Fri, Jul 24, 2020 at 8:35 AM Eric Christopher <echristo at gmail.com>
>> wrote:
>> >
>> > Hi Roman,
>>
>> > I'm seeing significant (5% or more) regressions in Eigen real's
>> benchmarks with this patch on x86 running with sse4.2 on skylake.
>> Interesting.
>>
>>
> (Correction Haswell).
>
>
>> > Likely this means that the previous code was handled in the backend,
>> but not this.
>> Or that some other transform somewhere else doesn't handle the case of
>> inverted predicate.
>>
>> > I've added Craig here as well for the x86 side of things.
>> It would be very helpful to have some preproducers.
>> In regressed cases, how does the final IR change?
>>
>>
> I don't have anything. I was speaking with Craig on Friday night and I
> think he might be looking at the Eigen benchmarks. If not, I can try to get
> something whittle down a bit more. This isn't urgent, but it's significant
> enough that we should all take a look as we get a chance.
>
>
>> > Did you end up running any performance analysis on generated code with
>> this?
>> Honestly, in this case, i did not.
>>
>>
> *nod* Probably running something is good, but this doesn't seem entirely
> unreasonable either.
>
> Just wanted to give a heads up for now.
>
> Thanks!
>
> -eric
>
>
>> > -eric
>> Roman
>>
>> > On Sat, Jul 4, 2020 at 8:13 AM Roman Lebedev via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>> >>
>> >>
>> >> Author: Roman Lebedev
>> >> Date: 2020-07-04T18:12:04+03:00
>> >> New Revision: c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248
>> >>
>> >> URL:
>> https://github.com/llvm/llvm-project/commit/c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248
>> >> DIFF:
>> https://github.com/llvm/llvm-project/commit/c3b8bd1eea5b74b6cd4a89f3c221bc2dfa891248.diff
>> >>
>> >> LOG: [InstCombine] Always try to invert non-canonical predicate of an
>> icmp
>> >>
>> >> Summary:
>> >> The actual transform i was going after was:
>> >> https://rise4fun.com/Alive/Tp9H
>> >> ```
>> >> Name: zz
>> >> Pre: isPowerOf2(C0) && isPowerOf2(C1) && C1 == C0
>> >> %t0 = and i8 %x, C0
>> >> %r = icmp eq i8 %t0, C1
>> >> =>
>> >> %t = icmp eq i8 %t0, 0
>> >> %r = xor i1 %t, -1
>> >>
>> >> Name: zz
>> >> Pre: isPowerOf2(C0)
>> >> %t0 = and i8 %x, C0
>> >> %r = icmp ne i8 %t0, 0
>> >> =>
>> >> %t = icmp eq i8 %t0, 0
>> >> %r = xor i1 %t, -1
>> >> ```
>> >> but as it can be seen from the current tests, we already canonicalize
>> most of it,
>> >> and we are only missing handling multi-use non-canonical icmp
>> predicates.
>> >>
>> >> If we have both `!=0` and `==0`, even though we can CSE them,
>> >> we end up being stuck with them. We should canonicalize to the `==0`.
>> >>
>> >> I believe this is one of the cleanup steps i'll need after
>> `-scalarizer`
>> >> if i end up proceeding with my WIP alloca promotion helper pass.
>> >>
>> >> Reviewers: spatel, jdoerfert, nikic
>> >>
>> >> Reviewed By: nikic
>> >>
>> >> Subscribers: zzheng, hiraditya, llvm-commits
>> >>
>> >> Tags: #llvm
>> >>
>> >> Differential Revision: https://reviews.llvm.org/D83139
>> >>
>> >> Added:
>> >>
>> >>
>> >> Modified:
>> >> llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
>> >> llvm/lib/Transforms/InstCombine/InstCombineInternal.h
>> >> llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
>> >> llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
>> >> llvm/test/ThinLTO/X86/cfi-devirt.ll
>> >>
>> llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
>> >> llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
>> >> llvm/test/Transforms/InstCombine/logical-select.ll
>> >> llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
>> >> llvm/test/Transforms/InstCombine/shift.ll
>> >> llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
>> >> llvm/test/Transforms/PGOProfile/chr.ll
>> >> llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll
>> >>
>> >> Removed:
>> >>
>> >>
>> >>
>> >>
>> ################################################################################
>> >> diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
>> b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
>> >> index 53a3af03e46f..31cd8e4510fa 100644
>> >> --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
>> >> +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
>> >> @@ -5283,6 +5283,47 @@ static ICmpInst
>> *canonicalizeCmpWithConstant(ICmpInst &I) {
>> >> return new ICmpInst(FlippedStrictness->first, Op0,
>> FlippedStrictness->second);
>> >> }
>> >>
>> >> +/// If we have a comparison with a non-canonical predicate, if we can
>> update
>> >> +/// all the users, invert the predicate and adjust all the users.
>> >> +static CmpInst *canonicalizeICmpPredicate(CmpInst &I) {
>> >> + // Is the predicate already canonical?
>> >> + CmpInst::Predicate Pred = I.getPredicate();
>> >> + if (isCanonicalPredicate(Pred))
>> >> + return nullptr;
>> >> +
>> >> + // Can all users be adjusted to predicate inversion?
>> >> + if (!canFreelyInvertAllUsersOf(&I, /*IgnoredUser=*/nullptr))
>> >> + return nullptr;
>> >> +
>> >> + // Ok, we can canonicalize comparison!
>> >> + // Let's first invert the comparison's predicate.
>> >> + I.setPredicate(CmpInst::getInversePredicate(Pred));
>> >> + I.setName(I.getName() + ".not");
>> >> +
>> >> + // And now let's adjust every user.
>> >> + for (User *U : I.users()) {
>> >> + switch (cast<Instruction>(U)->getOpcode()) {
>> >> + case Instruction::Select: {
>> >> + auto *SI = cast<SelectInst>(U);
>> >> + SI->swapValues();
>> >> + SI->swapProfMetadata();
>> >> + break;
>> >> + }
>> >> + case Instruction::Br:
>> >> + cast<BranchInst>(U)->swapSuccessors(); // swaps prof metadata
>> too
>> >> + break;
>> >> + case Instruction::Xor:
>> >> + U->replaceAllUsesWith(&I);
>> >> + break;
>> >> + default:
>> >> + llvm_unreachable("Got unexpected user - out of sync with "
>> >> + "canFreelyInvertAllUsersOf() ?");
>> >> + }
>> >> + }
>> >> +
>> >> + return &I;
>> >> +}
>> >> +
>> >> /// Integer compare with boolean values can always be turned into
>> bitwise ops.
>> >> static Instruction *canonicalizeICmpBool(ICmpInst &I,
>> >> InstCombiner::BuilderTy
>> &Builder) {
>> >> @@ -5521,8 +5562,11 @@ Instruction
>> *InstCombiner::visitICmpInst(ICmpInst &I) {
>> >> if (Instruction *Res = canonicalizeICmpBool(I, Builder))
>> >> return Res;
>> >>
>> >> - if (ICmpInst *NewICmp = canonicalizeCmpWithConstant(I))
>> >> - return NewICmp;
>> >> + if (Instruction *Res = canonicalizeCmpWithConstant(I))
>> >> + return Res;
>> >> +
>> >> + if (Instruction *Res = canonicalizeICmpPredicate(I))
>> >> + return Res;
>> >>
>> >> if (Instruction *Res = foldICmpWithConstant(I))
>> >> return Res;
>> >>
>> >> diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
>> b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
>> >> index 8caf580a3fd6..dd2f59be08e9 100644
>> >> --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
>> >> +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
>> >> @@ -215,18 +215,23 @@ static inline bool isFreeToInvert(Value *V, bool
>> WillInvertAllUses) {
>> >> }
>> >>
>> >> /// Given i1 V, can every user of V be freely adapted if V is changed
>> to !V ?
>> >> +/// InstCombine's canonicalizeICmpPredicate() must be kept in sync
>> with this fn.
>> >> ///
>> >> /// See also: isFreeToInvert()
>> >> static inline bool canFreelyInvertAllUsersOf(Value *V, Value
>> *IgnoredUser) {
>> >> // Look at every user of V.
>> >> - for (User *U : V->users()) {
>> >> - if (U == IgnoredUser)
>> >> + for (Use &U : V->uses()) {
>> >> + if (U.getUser() == IgnoredUser)
>> >> continue; // Don't consider this user.
>> >>
>> >> - auto *I = cast<Instruction>(U);
>> >> + auto *I = cast<Instruction>(U.getUser());
>> >> switch (I->getOpcode()) {
>> >> case Instruction::Select:
>> >> + if (U.getOperandNo() != 0) // Only if the value is used as
>> select cond.
>> >> + return false;
>> >> + break;
>> >> case Instruction::Br:
>> >> + assert(U.getOperandNo() == 0 && "Must be branching on that
>> value.");
>> >> break; // Free to invert by swapping true/false
>> values/destinations.
>> >> case Instruction::Xor: // Can invert 'xor' if it's a 'not', by
>> ignoring it.
>> >> if (!match(I, m_Not(m_Value())))
>> >>
>> >> diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
>> b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
>> >> index 8200310afa43..233fb3878ba7 100644
>> >> --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
>> >> +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
>> >> @@ -2532,21 +2532,7 @@ Instruction
>> *InstCombiner::visitSelectInst(SelectInst &SI) {
>> >> if (Instruction *I = canonicalizeScalarSelectOfVecs(SI, *this))
>> >> return I;
>> >>
>> >> - // Canonicalize a one-use integer compare with a non-canonical
>> predicate by
>> >> - // inverting the predicate and swapping the select operands. This
>> matches a
>> >> - // compare canonicalization for conditional branches.
>> >> - // TODO: Should we do the same for FP compares?
>> >> CmpInst::Predicate Pred;
>> >> - if (match(CondVal, m_OneUse(m_ICmp(Pred, m_Value(), m_Value()))) &&
>> >> - !isCanonicalPredicate(Pred)) {
>> >> - // Swap true/false values and condition.
>> >> - CmpInst *Cond = cast<CmpInst>(CondVal);
>> >> - Cond->setPredicate(CmpInst::getInversePredicate(Pred));
>> >> - SI.swapValues();
>> >> - SI.swapProfMetadata();
>> >> - Worklist.push(Cond);
>> >> - return &SI;
>> >> - }
>> >>
>> >> if (SelType->isIntOrIntVectorTy(1) &&
>> >> TrueVal->getType() == CondVal->getType()) {
>> >>
>> >> diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
>> b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
>> >> index 28dd92924b60..d1c1e5418825 100644
>> >> --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
>> >> +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
>> >> @@ -2755,9 +2755,9 @@ Instruction
>> *InstCombiner::visitBranchInst(BranchInst &BI) {
>> >> return replaceOperand(
>> >> BI, 0, ConstantInt::getFalse(BI.getCondition()->getType()));
>> >>
>> >> - // Canonicalize, for example, icmp_ne -> icmp_eq or fcmp_one ->
>> fcmp_oeq.
>> >> + // Canonicalize, for example, fcmp_one -> fcmp_oeq.
>> >> CmpInst::Predicate Pred;
>> >> - if (match(&BI, m_Br(m_OneUse(m_Cmp(Pred, m_Value(), m_Value())),
>> >> + if (match(&BI, m_Br(m_OneUse(m_FCmp(Pred, m_Value(), m_Value())),
>> >> m_BasicBlock(), m_BasicBlock())) &&
>> >> !isCanonicalPredicate(Pred)) {
>> >> // Swap destinations and condition.
>> >>
>> >> diff --git a/llvm/test/ThinLTO/X86/cfi-devirt.ll
>> b/llvm/test/ThinLTO/X86/cfi-devirt.ll
>> >> index 311bed084dee..61e0c166812c 100644
>> >> --- a/llvm/test/ThinLTO/X86/cfi-devirt.ll
>> >> +++ b/llvm/test/ThinLTO/X86/cfi-devirt.ll
>> >> @@ -110,10 +110,10 @@ cont2:
>> >>
>> >> ; Check that traps are conditional. Invalid TYPE_ID can cause
>> >> ; unconditional traps.
>> >> - ; CHECK-IR: br i1 {{.*}}, label %trap
>> >> + ; CHECK-IR: br i1 {{.*}}, label %trap, label %cont2
>> >>
>> >> ; We still have to call it as virtual.
>> >> - ; CHECK-IR: %call3 = tail call i32 %8
>> >> + ; CHECK-IR: %call3 = tail call i32 %7
>> >> %call3 = tail call i32 %8(%struct.A* nonnull %obj, i32 %call)
>> >> ret i32 %call3
>> >> }
>> >>
>> >> diff --git
>> a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
>> b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
>> >> index c4419a82c115..57390b376b50 100644
>> >> ---
>> a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
>> >> +++
>> b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll
>> >> @@ -8,8 +8,8 @@ declare void @use1(i1)
>> >> define i8 @p0(i8 %x, i8 %v0, i8 %v1) {
>> >> ; CHECK-LABEL: @p0(
>> >> ; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1
>> >> -; CHECK-NEXT: [[T1:%.*]] = icmp eq i8 [[T0]], 0
>> >> -; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V1:%.*]], i8
>> [[V0:%.*]], !prof !0
>> >> +; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0
>> >> +; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8
>> [[V0:%.*]], !prof !0
>> >> ; CHECK-NEXT: ret i8 [[R]]
>> >> ;
>> >> %t0 = and i8 %x, 1
>> >> @@ -20,8 +20,8 @@ define i8 @p0(i8 %x, i8 %v0, i8 %v1) {
>> >> define i8 @p1(i8 %x, i8 %v0, i8 %v1) {
>> >> ; CHECK-LABEL: @p1(
>> >> ; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1
>> >> -; CHECK-NEXT: [[T1:%.*]] = icmp eq i8 [[T0]], 0
>> >> -; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V1:%.*]], i8
>> [[V0:%.*]]
>> >> +; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0
>> >> +; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8
>> [[V0:%.*]]
>> >> ; CHECK-NEXT: ret i8 [[R]]
>> >> ;
>> >> %t0 = and i8 %x, 1
>> >> @@ -51,14 +51,14 @@ define i8 @t3(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8
>> %v3, i8* %out, i1 %c) {
>> >> ; CHECK-LABEL: @t3(
>> >> ; CHECK-NEXT: bb0:
>> >> ; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1
>> >> -; CHECK-NEXT: [[T1:%.*]] = icmp ne i8 [[T0]], 0
>> >> +; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0
>> >> ; CHECK-NEXT: br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
>> >> ; CHECK: bb1:
>> >> -; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8
>> [[V1:%.*]]
>> >> +; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8
>> [[V0:%.*]]
>> >> ; CHECK-NEXT: store i8 [[R0]], i8* [[OUT:%.*]], align 1
>> >> ; CHECK-NEXT: br label [[BB2]]
>> >> ; CHECK: bb2:
>> >> -; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1]], i8 [[V2:%.*]], i8
>> [[V3:%.*]]
>> >> +; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1_NOT]], i8 [[V3:%.*]], i8
>> [[V2:%.*]]
>> >> ; CHECK-NEXT: ret i8 [[R1]]
>> >> ;
>> >> bb0:
>> >> @@ -76,10 +76,10 @@ bb2:
>> >> define i8 @t4(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8 %v3, i8* %out) {
>> >> ; CHECK-LABEL: @t4(
>> >> ; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1
>> >> -; CHECK-NEXT: [[T1:%.*]] = icmp ne i8 [[T0]], 0
>> >> -; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8
>> [[V1:%.*]]
>> >> +; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0
>> >> +; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8
>> [[V0:%.*]]
>> >> ; CHECK-NEXT: store i8 [[R0]], i8* [[OUT:%.*]], align 1
>> >> -; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1]], i8 [[V2:%.*]], i8
>> [[V3:%.*]]
>> >> +; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1_NOT]], i8 [[V3:%.*]], i8
>> [[V2:%.*]]
>> >> ; CHECK-NEXT: ret i8 [[R1]]
>> >> ;
>> >> %t0 = and i8 %x, 1
>> >> @@ -112,8 +112,8 @@ define i8 @n6(i8 %x, i8 %v0, i8 %v1) {
>> >> define i8 @n7(i8 %x, i8 %v0, i8 %v1) {
>> >> ; CHECK-LABEL: @n7(
>> >> ; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1
>> >> -; CHECK-NEXT: [[T1:%.*]] = icmp eq i8 [[T0]], 0
>> >> -; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8
>> [[V1:%.*]]
>> >> +; CHECK-NEXT: [[T1_NOT_NOT:%.*]] = icmp eq i8 [[T0]], 0
>> >> +; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT_NOT]], i8 [[V0:%.*]],
>> i8 [[V1:%.*]]
>> >> ; CHECK-NEXT: ret i8 [[R]]
>> >> ;
>> >> %t0 = and i8 %x, 1
>> >>
>> >> diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
>> b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
>> >> index a5b148ebd796..31540e600f9f 100644
>> >> --- a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
>> >> +++ b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
>> >> @@ -13,16 +13,16 @@ define i32 @sterix(i32, i8, i64) {
>> >> ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], [[SH_PROM]]
>> >> ; CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[SHR]] to i64
>> >> ; CHECK-NEXT: [[MUL3:%.*]] = mul nuw nsw i64 [[CONV]], [[CONV2]]
>> >> -; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i64 [[MUL3]], 4294967295
>> >> -; CHECK-NEXT: br i1 [[TMP3]], label [[LOR_END:%.*]], label
>> [[LOR_RHS:%.*]]
>> >> +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[MUL3]], 4294967296
>> >> +; CHECK-NEXT: br i1 [[TMP3]], label [[LOR_RHS:%.*]], label
>> [[LOR_END:%.*]]
>> >> ; CHECK: lor.rhs:
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i64 [[MUL3]], [[TMP2]]
>> >> ; CHECK-NEXT: [[CONV4:%.*]] = trunc i64 [[AND]] to i32
>> >> -; CHECK-NEXT: [[TOBOOL7:%.*]] = icmp eq i32 [[CONV4]], 0
>> >> -; CHECK-NEXT: [[PHI_CAST:%.*]] = zext i1 [[TOBOOL7]] to i32
>> >> +; CHECK-NEXT: [[TOBOOL7_NOT:%.*]] = icmp eq i32 [[CONV4]], 0
>> >> +; CHECK-NEXT: [[PHITMP:%.*]] = zext i1 [[TOBOOL7_NOT]] to i32
>> >> ; CHECK-NEXT: br label [[LOR_END]]
>> >> ; CHECK: lor.end:
>> >> -; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [
>> [[PHI_CAST]], [[LOR_RHS]] ]
>> >> +; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [
>> [[PHITMP]], [[LOR_RHS]] ]
>> >> ; CHECK-NEXT: ret i32 [[TMP4]]
>> >> ;
>> >> entry:
>> >>
>> >> diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll
>> b/llvm/test/Transforms/InstCombine/logical-select.ll
>> >> index e14e2bf964d9..2f532be03fbf 100644
>> >> --- a/llvm/test/Transforms/InstCombine/logical-select.ll
>> >> +++ b/llvm/test/Transforms/InstCombine/logical-select.ll
>> >> @@ -19,8 +19,8 @@ define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {
>> >>
>> >> define i32 @bar(i32 %a, i32 %b, i32 %c, i32 %d) {
>> >> ; CHECK-LABEL: @bar(
>> >> -; CHECK-NEXT: [[E:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
>> >> -; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[E]], i32 [[C:%.*]], i32
>> [[D:%.*]]
>> >> +; CHECK-NEXT: [[E_NOT:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
>> >> +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[E_NOT]], i32 [[C:%.*]],
>> i32 [[D:%.*]]
>> >> ; CHECK-NEXT: ret i32 [[TMP1]]
>> >> ;
>> >> %e = icmp slt i32 %a, %b
>> >> @@ -69,8 +69,8 @@ define i32 @fold_inverted_icmp_preds(i32 %a, i32 %b,
>> i32 %c, i32 %d) {
>> >> ; CHECK-LABEL: @fold_inverted_icmp_preds(
>> >> ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
>> >> ; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 [[C:%.*]],
>> i32 0
>> >> -; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B]]
>> >> -; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 0, i32
>> [[D:%.*]]
>> >> +; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp slt i32 [[A]], [[B]]
>> >> +; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2_NOT]], i32 0, i32
>> [[D:%.*]]
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]
>> >> ; CHECK-NEXT: ret i32 [[OR]]
>> >> ;
>> >> @@ -88,8 +88,8 @@ define i32 @fold_inverted_icmp_preds_reverse(i32 %a,
>> i32 %b, i32 %c, i32 %d) {
>> >> ; CHECK-LABEL: @fold_inverted_icmp_preds_reverse(
>> >> ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
>> >> ; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32
>> [[C:%.*]]
>> >> -; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B]]
>> >> -; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i32 [[D:%.*]],
>> i32 0
>> >> +; CHECK-NEXT: [[CMP2_NOT:%.*]] = icmp slt i32 [[A]], [[B]]
>> >> +; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2_NOT]], i32
>> [[D:%.*]], i32 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]
>> >> ; CHECK-NEXT: ret i32 [[OR]]
>> >> ;
>> >> @@ -124,8 +124,8 @@ define i32 @fold_inverted_fcmp_preds(float %a,
>> float %b, i32 %c, i32 %d) {
>> >>
>> >> define <2 x i32> @fold_inverted_icmp_vector_preds(<2 x i32> %a, <2 x
>> i32> %b, <2 x i32> %c, <2 x i32> %d) {
>> >> ; CHECK-LABEL: @fold_inverted_icmp_vector_preds(
>> >> -; CHECK-NEXT: [[CMP1:%.*]] = icmp eq <2 x i32> [[A:%.*]], [[B:%.*]]
>> >> -; CHECK-NEXT: [[SEL1:%.*]] = select <2 x i1> [[CMP1]], <2 x i32>
>> zeroinitializer, <2 x i32> [[C:%.*]]
>> >> +; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq <2 x i32> [[A:%.*]],
>> [[B:%.*]]
>> >> +; CHECK-NEXT: [[SEL1:%.*]] = select <2 x i1> [[CMP1_NOT]], <2 x
>> i32> zeroinitializer, <2 x i32> [[C:%.*]]
>> >> ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq <2 x i32> [[A]], [[B]]
>> >> ; CHECK-NEXT: [[SEL2:%.*]] = select <2 x i1> [[CMP2]], <2 x i32>
>> [[D:%.*]], <2 x i32> zeroinitializer
>> >> ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[SEL1]], [[SEL2]]
>> >> @@ -535,9 +535,9 @@ define <4 x i32> @vec_sel_xor_multi_use(<4 x i32>
>> %a, <4 x i32> %b, <4 x i1> %c)
>> >>
>> >> define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) {
>> >> ; CHECK-LABEL: @allSignBits(
>> >> -; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[COND:%.*]], -1
>> >> -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[FVAL:%.*]],
>> i32 [[TVAL:%.*]]
>> >> -; CHECK-NEXT: ret i32 [[TMP2]]
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp slt i32 [[COND:%.*]], 0
>> >> +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[DOTNOT]], i32
>> [[TVAL:%.*]], i32 [[FVAL:%.*]]
>> >> +; CHECK-NEXT: ret i32 [[TMP1]]
>> >> ;
>> >> %bitmask = ashr i32 %cond, 31
>> >> %not_bitmask = xor i32 %bitmask, -1
>> >> @@ -549,9 +549,9 @@ define i32 @allSignBits(i32 %cond, i32 %tval, i32
>> %fval) {
>> >>
>> >> define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x
>> i8> %fval) {
>> >> ; CHECK-LABEL: @allSignBits_vec(
>> >> -; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8
>> -1, i8 -1, i8 -1, i8 -1>
>> >> -; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8>
>> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]]
>> >> -; CHECK-NEXT: ret <4 x i8> [[TMP2]]
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8
>> -1, i8 -1, i8 -1, i8 -1>
>> >> +; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[DOTNOT]], <4 x i8>
>> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]]
>> >> +; CHECK-NEXT: ret <4 x i8> [[TMP1]]
>> >> ;
>> >> %bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7>
>> >> %not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1>
>> >>
>> >> diff --git
>> a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
>> b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
>> >> index d46227d74db3..6eccbecd1d4d 100644
>> >> --- a/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
>> >> +++ b/llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
>> >> @@ -153,9 +153,9 @@ define <2 x i32>
>> @select_icmp_ne_0_and_4096_or_4096_vec(<2 x i32> %x, <2 x i32>
>> >> define i32 @select_icmp_ne_0_and_4096_xor_4096(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_4096_xor_4096(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 4096
>> >> @@ -168,9 +168,9 @@ define i32 @select_icmp_ne_0_and_4096_xor_4096(i32
>> %x, i32 %y) {
>> >> define i32 @select_icmp_ne_0_and_4096_and_not_4096(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_4096_and_not_4096(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 4096
>> >> @@ -311,9 +311,9 @@ define i32 @select_icmp_ne_0_and_4096_or_32(i32
>> %x, i32 %y) {
>> >> define i32 @select_icmp_ne_0_and_4096_xor_32(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_4096_xor_32(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 32
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 4096
>> >> @@ -326,9 +326,9 @@ define i32 @select_icmp_ne_0_and_4096_xor_32(i32
>> %x, i32 %y) {
>> >> define i32 @select_icmp_ne_0_and_4096_and_not_32(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_4096_and_not_32(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -33
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 4096
>> >> @@ -371,9 +371,9 @@ define <2 x i32>
>> @select_icmp_ne_0_and_32_or_4096_vec(<2 x i32> %x, <2 x i32> %y
>> >> define i32 @select_icmp_ne_0_and_32_xor_4096(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_32_xor_4096(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 32
>> >> @@ -386,9 +386,9 @@ define i32 @select_icmp_ne_0_and_32_xor_4096(i32
>> %x, i32 %y) {
>> >> define i32 @select_icmp_ne_0_and_32_and_not_4096(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_32_and_not_4096(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 32
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 32
>> >> @@ -401,9 +401,9 @@ define i32
>> @select_icmp_ne_0_and_32_and_not_4096(i32 %x, i32 %y) {
>> >> define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_or_8(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], 8
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[OR]], i8
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i8 [[OR]],
>> i8 [[Y]]
>> >> ; CHECK-NEXT: ret i8 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 1073741824
>> >> @@ -416,9 +416,9 @@ define i8
>> @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) {
>> >> define i8 @select_icmp_ne_0_and_1073741824_xor_8(i32 %x, i8 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_xor_8(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[Y:%.*]], 8
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[XOR]], i8
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i8 [[XOR]],
>> i8 [[Y]]
>> >> ; CHECK-NEXT: ret i8 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 1073741824
>> >> @@ -431,9 +431,9 @@ define i8
>> @select_icmp_ne_0_and_1073741824_xor_8(i32 %x, i8 %y) {
>> >> define i8 @select_icmp_ne_0_and_1073741824_and_not_8(i32 %x, i8 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_and_not_8(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741824
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i8 [[Y:%.*]], -9
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i8 [[AND2]], i8
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i8 [[AND2]],
>> i8 [[Y]]
>> >> ; CHECK-NEXT: ret i8 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 1073741824
>> >> @@ -446,9 +446,9 @@ define i8
>> @select_icmp_ne_0_and_1073741824_and_not_8(i32 %x, i8 %y) {
>> >> define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_8_or_1073741824(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i8 [[AND]], 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 1073741824
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i8 %x, 8
>> >> @@ -461,9 +461,9 @@ define i32
>> @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) {
>> >> define i32 @select_icmp_ne_0_and_8_xor_1073741824(i8 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_8_xor_1073741824(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i8 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 1073741824
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i8 %x, 8
>> >> @@ -476,9 +476,9 @@ define i32
>> @select_icmp_ne_0_and_8_xor_1073741824(i8 %x, i32 %y) {
>> >> define i32 @select_icmp_ne_0_and_8_and_not_1073741824(i8 %x, i32 %y) {
>> >> ; CHECK-LABEL: @select_icmp_ne_0_and_8_and_not_1073741824(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i8 [[X:%.*]], 8
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i8 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -1073741825
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i8 %x, 8
>> >> @@ -731,9 +731,9 @@ define <2 x i32> @test69vec(<2 x i32> %x, <2 x
>> i32> %y) {
>> >> define i32 @test69_xor(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @test69_xor(
>> >> ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp sgt i8 [[TMP1]], -1
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[XOR]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 128
>> >> @@ -746,9 +746,9 @@ define i32 @test69_xor(i32 %x, i32 %y) {
>> >> define i32 @test69_and(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @test69_and(
>> >> ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp sgt i8 [[TMP1]], -1
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], 2
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[AND2]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: ret i32 [[SELECT]]
>> >> ;
>> >> %and = and i32 %x, 128
>> >> @@ -892,9 +892,9 @@ define i32 @no_shift_xor_multiuse_or(i32 %x, i32
>> %y) {
>> >> define i32 @no_shift_xor_multiuse_xor(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_xor(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -909,9 +909,9 @@ define i32 @no_shift_xor_multiuse_xor(i32 %x, i32
>> %y) {
>> >> define i32 @no_shift_xor_multiuse_and(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_and(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -926,9 +926,9 @@ define i32 @no_shift_xor_multiuse_and(i32 %x, i32
>> %y) {
>> >> define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_or(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[OR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[OR]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -943,9 +943,9 @@ define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) {
>> >> define i32 @shift_xor_multiuse_xor(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_xor(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32
>> [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[XOR]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -960,9 +960,9 @@ define i32 @shift_xor_multiuse_xor(i32 %x, i32 %y)
>> {
>> >> define i32 @shift_xor_multiuse_and(i32 %x, i32 %y) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_and(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2049
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[AND2]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[AND2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1090,10 +1090,10 @@ define i32
>> @no_shift_no_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w
>> >> define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w)
>> {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_cmp(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096
>> >> ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[W:%.*]],
>> i32 [[Z:%.*]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1109,10 +1109,10 @@ define i32 @no_shift_xor_multiuse_cmp(i32 %x,
>> i32 %y, i32 %z, i32 %w) {
>> >> define i32 @no_shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32
>> %z, i32 %w) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_cmp_with_xor(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[XOR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1128,10 +1128,10 @@ define i32
>> @no_shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @no_shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32
>> %z, i32 %w) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_cmp_with_and(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[AND2]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1147,10 +1147,10 @@ define i32
>> @no_shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_cmp(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[OR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1166,10 +1166,10 @@ define i32 @shift_xor_multiuse_cmp(i32 %x, i32
>> %y, i32 %z, i32 %w) {
>> >> define i32 @shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z,
>> i32 %w) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_cmp_with_xor(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[XOR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1185,10 +1185,10 @@ define i32
>> @shift_xor_multiuse_cmp_with_xor(i32 %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @shift_xor_multiuse_cmp_with_and(i32 %x, i32 %y, i32 %z,
>> i32 %w) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_cmp_with_and(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -2049
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[AND2]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: ret i32 [[RES]]
>> >> ;
>> >> @@ -1330,10 +1330,10 @@ define i32
>> @no_shift_no_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @no_shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32
>> %w) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_cmp_or(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[OR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
>> >> ; CHECK-NEXT: ret i32 [[RES2]]
>> >> @@ -1351,10 +1351,10 @@ define i32 @no_shift_xor_multiuse_cmp_or(i32
>> %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @no_shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32
>> %w) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_cmp_xor(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[XOR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
>> >> ; CHECK-NEXT: ret i32 [[RES2]]
>> >> @@ -1372,10 +1372,10 @@ define i32 @no_shift_xor_multiuse_cmp_xor(i32
>> %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @no_shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32
>> %w) {
>> >> ; CHECK-LABEL: @no_shift_xor_multiuse_cmp_and(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], -4097
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[AND2]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
>> >> ; CHECK-NEXT: ret i32 [[RES2]]
>> >> @@ -1393,10 +1393,10 @@ define i32 @no_shift_xor_multiuse_cmp_and(i32
>> %x, i32 %y, i32 %z, i32 %w) {
>> >> define i32 @shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w)
>> {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_cmp_or(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[OR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[OR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]]
>> >> ; CHECK-NEXT: ret i32 [[RES2]]
>> >> @@ -1414,10 +1414,10 @@ define i32 @shift_xor_multiuse_cmp_or(i32 %x,
>> i32 %y, i32 %z, i32 %w) {
>> >> define i32 @shift_xor_multiuse_cmp_xor(i32 %x, i32 %y, i32 %z, i32
>> %w) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_cmp_xor(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[XOR]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32 [[XOR]],
>> i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[XOR]]
>> >> ; CHECK-NEXT: ret i32 [[RES2]]
>> >> @@ -1435,10 +1435,10 @@ define i32 @shift_xor_multiuse_cmp_xor(i32 %x,
>> i32 %y, i32 %z, i32 %w) {
>> >> define i32 @shift_xor_multiuse_cmp_and(i32 %x, i32 %y, i32 %z, i32
>> %w) {
>> >> ; CHECK-LABEL: @shift_xor_multiuse_cmp_and(
>> >> ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096
>> >> -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
>> >> +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[AND]], 0
>> >> ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[Y:%.*]], 2048
>> >> -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32
>> [[AND2]]
>> >> -; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]],
>> i32 [[W:%.*]]
>> >> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP_NOT]], i32
>> [[AND2]], i32 [[Y]]
>> >> +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP_NOT]], i32
>> [[W:%.*]], i32 [[Z:%.*]]
>> >> ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[SELECT]], [[SELECT2]]
>> >> ; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[AND2]]
>> >> ; CHECK-NEXT: ret i32 [[RES2]]
>> >>
>> >> diff --git a/llvm/test/Transforms/InstCombine/shift.ll
>> b/llvm/test/Transforms/InstCombine/shift.ll
>> >> index 52b7c87cb063..714a08d247a2 100644
>> >> --- a/llvm/test/Transforms/InstCombine/shift.ll
>> >> +++ b/llvm/test/Transforms/InstCombine/shift.ll
>> >> @@ -428,8 +428,8 @@ define i8 @test28a(i8 %x, i8 %y) {
>> >> ; CHECK-LABEL: @test28a(
>> >> ; CHECK-NEXT: entry:
>> >> ; CHECK-NEXT: [[I1:%.*]] = lshr i8 [[X:%.*]], 7
>> >> -; CHECK-NEXT: [[COND1:%.*]] = icmp slt i8 [[X]], 0
>> >> -; CHECK-NEXT: br i1 [[COND1]], label [[BB1:%.*]], label [[BB2:%.*]]
>> >> +; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X]], -1
>> >> +; CHECK-NEXT: br i1 [[COND1_NOT]], label [[BB2:%.*]], label
>> [[BB1:%.*]]
>> >> ; CHECK: bb1:
>> >> ; CHECK-NEXT: ret i8 [[I1]]
>> >> ; CHECK: bb2:
>> >>
>> >> diff --git
>> a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
>> b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
>> >> index 75bad6813b0e..7be217b06aae 100644
>> >> --- a/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
>> >> +++ b/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
>> >> @@ -1,8 +1,8 @@
>> >> ; RUN: opt < %s -loop-unroll -unroll-runtime=true
>> -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true
>> -verify-loop-lcssa -verify-dom-info -verify-loop-info -S | FileCheck %s
>> -check-prefix=EPILOG-NO-IC
>> >> ; RUN: opt < %s -loop-unroll -unroll-runtime=true
>> -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true
>> -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S |
>> FileCheck %s -check-prefix=EPILOG
>> >> -; RUN: opt < %s -loop-unroll -unroll-runtime -unroll-count=2
>> -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true
>> -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine
>> >> +; RUN: opt < %s -loop-unroll -unroll-runtime -unroll-count=2
>> -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true
>> -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S
>> >> ; RUN: opt < %s -loop-unroll -unroll-runtime=true
>> -unroll-runtime-epilog=false -unroll-runtime-multi-exit=true
>> -verify-loop-lcssa -verify-dom-info -verify-loop-info -instcombine -S |
>> FileCheck %s -check-prefix=PROLOG
>> >> -; RUN: opt < %s -loop-unroll -unroll-runtime
>> -unroll-runtime-epilog=false -unroll-count=2
>> -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info
>> -verify-loop-info -instcombine
>> >> +; RUN: opt < %s -loop-unroll -unroll-runtime
>> -unroll-runtime-epilog=false -unroll-count=2
>> -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info
>> -verify-loop-info -instcombine -S
>> >>
>> >> ; REQUIRES: asserts
>> >>
>> >> @@ -23,12 +23,12 @@ define void @test1(i64 %trip, i1 %cond) {
>> >> ; EPILOG-NEXT: br label [[LOOP_HEADER:%.*]]
>> >> ; EPILOG: loop_latch.epil:
>> >> ; EPILOG-NEXT: %epil.iter.sub = add i64 %epil.iter, -1
>> >> -; EPILOG-NEXT: %epil.iter.cmp = icmp eq i64 %epil.iter.sub, 0
>> >> -; EPILOG-NEXT: br i1 %epil.iter.cmp, label
>> %exit2.loopexit.epilog-lcssa, label %loop_header.epil
>> >> +; EPILOG-NEXT: %epil.iter.cmp.not = icmp eq i64 %epil.iter.sub, 0
>> >> +; EPILOG-NEXT: br i1 %epil.iter.cmp.not, label
>> %exit2.loopexit.epilog-lcssa, label %loop_header.epil
>> >> ; EPILOG: loop_latch.7:
>> >> ; EPILOG-NEXT: %niter.nsub.7 = add i64 %niter, -8
>> >> -; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.nsub.7, 0
>> >> -; EPILOG-NEXT: br i1 %niter.ncmp.7, label
>> %exit2.loopexit.unr-lcssa.loopexit, label %loop_header
>> >> +; EPILOG-NEXT: %niter.ncmp.7.not = icmp eq i64 %niter.nsub.7, 0
>> >> +; EPILOG-NEXT: br i1 %niter.ncmp.7.not, label
>> %exit2.loopexit.unr-lcssa.loopexit, label %loop_header
>> >>
>> >> ; PROLOG: test1(
>> >> ; PROLOG-NEXT: entry:
>> >> @@ -43,12 +43,12 @@ define void @test1(i64 %trip, i1 %cond) {
>> >> ; PROLOG: loop_latch.prol:
>> >> ; PROLOG-NEXT: %iv_next.prol = add i64 %iv.prol, 1
>> >> ; PROLOG-NEXT: %prol.iter.sub = add i64 %prol.iter, -1
>> >> -; PROLOG-NEXT: %prol.iter.cmp = icmp eq i64 %prol.iter.sub, 0
>> >> -; PROLOG-NEXT: br i1 %prol.iter.cmp, label
>> %loop_header.prol.loopexit.unr-lcssa, label %loop_header.prol
>> >> +; PROLOG-NEXT: %prol.iter.cmp.not = icmp eq i64 %prol.iter.sub, 0
>> >> +; PROLOG-NEXT: br i1 %prol.iter.cmp.not, label
>> %loop_header.prol.loopexit.unr-lcssa, label %loop_header.prol
>> >> ; PROLOG: loop_latch.7:
>> >> ; PROLOG-NEXT: %iv_next.7 = add i64 %iv, 8
>> >> -; PROLOG-NEXT: %cmp.7 = icmp eq i64 %iv_next.7, %trip
>> >> -; PROLOG-NEXT: br i1 %cmp.7, label %exit2.loopexit.unr-lcssa,
>> label %loop_header
>> >> +; PROLOG-NEXT: %cmp.7.not = icmp eq i64 %iv_next.7, %trip
>> >> +; PROLOG-NEXT: br i1 %cmp.7.not, label %exit2.loopexit.unr-lcssa,
>> label %loop_header
>> >> entry:
>> >> br label %loop_header
>> >>
>> >> @@ -157,8 +157,8 @@ define void @test3(i64 %trip, i64 %add) {
>> >> ; EPILOG: loop_latch.7:
>> >> ; EPILOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
>> >> ; EPILOG-NEXT: %niter.nsub.7 = add i64 %niter, -8
>> >> -; EPILOG-NEXT: %niter.ncmp.7 = icmp eq i64 %niter.nsub.7, 0
>> >> -; EPILOG-NEXT: br i1 %niter.ncmp.7, label
>> %exit2.loopexit.unr-lcssa.loopexit, label %loop_header
>> >> +; EPILOG-NEXT: %niter.ncmp.7.not = icmp eq i64 %niter.nsub.7, 0
>> >> +; EPILOG-NEXT: br i1 %niter.ncmp.7.not, label
>> %exit2.loopexit.unr-lcssa.loopexit, label %loop_header
>> >>
>> >> ; PROLOG: test3(
>> >> ; PROLOG-NEXT: entry:
>> >> @@ -174,8 +174,8 @@ define void @test3(i64 %trip, i64 %add) {
>> >> ; PROLOG: loop_latch.7:
>> >> ; PROLOG-NEXT: %iv_next.7 = add nuw nsw i64 %iv, 8
>> >> ; PROLOG-NEXT: %sum.next.7 = add i64 %sum.next.6, %add
>> >> -; PROLOG-NEXT: %cmp.7 = icmp eq i64 %iv_next.7, %trip
>> >> -; PROLOG-NEXT: br i1 %cmp.7, label %exit2.loopexit.unr-lcssa,
>> label %loop_header
>> >> +; PROLOG-NEXT: %cmp.7.not = icmp eq i64 %iv_next.7, %trip
>> >> +; PROLOG-NEXT: br i1 %cmp.7.not, label %exit2.loopexit.unr-lcssa,
>> label %loop_header
>> >> entry:
>> >> br label %loop_header
>> >>
>> >> @@ -575,8 +575,8 @@ define void @test8() {
>> >> ; PROLOG: test8(
>> >> ; PROLOG: outerloop:
>> >> ; PROLOG-NEXT: phi i64 [ 3, %bb ], [ 0, %outerloop.loopexit ]
>> >> -; PROLOG: %lcmp.mod = icmp eq i64
>> >> -; PROLOG-NEXT: br i1 %lcmp.mod, label %innerH.prol.loopexit, label
>> %innerH.prol.preheader
>> >> +; PROLOG: %lcmp.mod.not = icmp eq i64
>> >> +; PROLOG-NEXT: br i1 %lcmp.mod.not, label %innerH.prol.loopexit,
>> label %innerH.prol.preheader
>> >> ; PROLOG: latch.6:
>> >> ; PROLOG-NEXT: br i1 false, label %outerloop.loopexit.loopexit, label
>> %latch.7
>> >> ; PROLOG: latch.7:
>> >> @@ -613,7 +613,7 @@ define i8 addrspace(1)* @test9(i8* nocapture
>> readonly %arg, i32 %n) {
>> >> ; PROLOG-NEXT: %phi.prol = phi i64 [ 0, %header.prol.preheader ], [
>> %iv.next.prol, %latch.prol ]
>> >> ; PROLOG: latch.prol:
>> >> ; PROLOG-NOT: trip
>> >> -; PROLOG: br i1 %prol.iter.cmp, label
>> %header.prol.loopexit.unr-lcssa, label %header.prol
>> >> +; PROLOG: br i1 %prol.iter.cmp.not, label
>> %header.prol.loopexit.unr-lcssa, label %header.prol
>> >> bb:
>> >> br label %outerloopHdr
>> >>
>> >>
>> >> diff --git a/llvm/test/Transforms/PGOProfile/chr.ll
>> b/llvm/test/Transforms/PGOProfile/chr.ll
>> >> index 9a6477aeb101..e2161d617022 100644
>> >> --- a/llvm/test/Transforms/PGOProfile/chr.ll
>> >> +++ b/llvm/test/Transforms/PGOProfile/chr.ll
>> >> @@ -36,15 +36,15 @@ define void @test_chr_1(i32* %i) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> ; CHECK: bb1.nonchr:
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> @@ -109,22 +109,22 @@ define void @test_chr_1_1(i32* %i) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB5:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> ; CHECK: bb1.nonchr:
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB2_NONCHR:%.*]], label
>> [[BB3_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label
>> [[BB3_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> ; CHECK-NEXT: call void @bar()
>> >> ; CHECK-NEXT: br label [[BB3_NONCHR]]
>> >> ; CHECK: bb3.nonchr:
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 4
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP8]], label [[BB5]], label
>> [[BB4_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 4
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP7]], label [[BB5]], label
>> [[BB4_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb4.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB5]]
>> >> @@ -195,16 +195,16 @@ define void @test_chr_2(i32* %i) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB4:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 255
>> >> -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP4]], label [[BB4]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB4]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB2_NONCHR:%.*]], label
>> [[BB1_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 1
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label
>> [[BB1_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP8]], label [[BB4]], label
>> [[BB3_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP7]], label [[BB4]], label
>> [[BB3_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb3.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB4]]
>> >> @@ -288,38 +288,38 @@ define void @test_chr_3(i32* %i) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> ; CHECK: bb1.nonchr:
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 12
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 12
>> >> -; CHECK-NEXT: br i1 [[TMP9]], label [[BB4:%.*]], label
>> [[BB3_SPLIT_NONCHR:%.*]], !prof !15
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 12
>> >> +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 12
>> >> +; CHECK-NEXT: br i1 [[TMP8]], label [[BB4:%.*]], label
>> [[BB3_SPLIT_NONCHR:%.*]], !prof !15
>> >> ; CHECK: bb4:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB7:%.*]]
>> >> ; CHECK: bb3.split.nonchr:
>> >> -; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP7]], 4
>> >> -; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP11]], label [[BB5_NONCHR:%.*]], label
>> [[BB4_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP6]], 4
>> >> +; CHECK-NEXT: [[DOTNOT1:%.*]] = icmp eq i32 [[TMP9]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT1]], label [[BB5_NONCHR:%.*]], label
>> [[BB4_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb4.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB5_NONCHR]]
>> >> ; CHECK: bb5.nonchr:
>> >> -; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP7]], 8
>> >> -; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP13]], label [[BB7]], label
>> [[BB6_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP6]], 8
>> >> +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP11]], label [[BB7]], label
>> [[BB6_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb6.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB7]]
>> >> @@ -396,12 +396,12 @@ define i32 @test_chr_4(i32* %i, i32 %sum0) !prof
>> !14 {
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SUM0]], 42
>> >> ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP6]], i32
>> [[SUM0]], i32 [[TMP4]], !prof !16
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[SUM1_NONCHR]], 43
>> >> -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP8]], i32
>> [[SUM1_NONCHR]], i32 [[TMP9]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> +; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[DOTNOT]], i32
>> [[SUM0]], i32 [[TMP4]], !prof !16
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> +; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1_NONCHR]], 43
>> >> +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP7]], i32
>> [[SUM1_NONCHR]], i32 [[TMP8]], !prof !16
>> >> ; CHECK-NEXT: ret i32 [[SUM2_NONCHR]]
>> >> ;
>> >> entry:
>> >> @@ -455,24 +455,24 @@ define i32 @test_chr_5(i32* %i, i32 %sum0) !prof
>> !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 255
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[SUM0]], 42
>> >> -; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP8]], i32
>> [[SUM0]], i32 [[TMP9]], !prof !16
>> >> -; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
>> >> -; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[SUM1_NONCHR]], 43
>> >> -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP11]], i32
>> [[SUM1_NONCHR]], i32 [[TMP12]], !prof !16
>> >> -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP0]], 4
>> >> -; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0
>> >> -; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[TMP0]], 8
>> >> -; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
>> >> -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44,
>> i32 88
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 1
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> +; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM0]], 42
>> >> +; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP7]], i32
>> [[SUM0]], i32 [[TMP8]], !prof !16
>> >> +; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
>> >> +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[SUM1_NONCHR]], 43
>> >> +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP10]], i32
>> [[SUM1_NONCHR]], i32 [[TMP11]], !prof !16
>> >> +; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP0]], 4
>> >> +; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0
>> >> +; CHECK-NEXT: [[TMP14:%.*]] = and i32 [[TMP0]], 8
>> >> +; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0
>> >> +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP15]], i32 44,
>> i32 88
>> >> ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]],
>> [[SUM4_NONCHR_V]]
>> >> -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP14]], i32
>> [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
>> >> +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP13]], i32
>> [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [
>> [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
>> >> @@ -555,24 +555,24 @@ define i32 @test_chr_5_1(i32* %i, i32 %sum0)
>> !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP0]], 255
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP9]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP8]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> -; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
>> >> -; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[SUM0]], 42
>> >> -; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP11]], i32
>> [[SUM0]], i32 [[TMP12]], !prof !16
>> >> -; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0
>> >> -; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[SUM1_NONCHR]], 43
>> >> -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP14]], i32
>> [[SUM1_NONCHR]], i32 [[TMP15]], !prof !16
>> >> -; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[SUM0]], 4
>> >> -; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 0
>> >> -; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[TMP0]], 8
>> >> -; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[TMP18]], 0
>> >> -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP19]], i32 44,
>> i32 88
>> >> +; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP0]], 1
>> >> +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
>> >> +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[SUM0]], 42
>> >> +; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP10]], i32
>> [[SUM0]], i32 [[TMP11]], !prof !16
>> >> +; CHECK-NEXT: [[TMP12:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], 0
>> >> +; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[SUM1_NONCHR]], 43
>> >> +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP13]], i32
>> [[SUM1_NONCHR]], i32 [[TMP14]], !prof !16
>> >> +; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[SUM0]], 4
>> >> +; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0
>> >> +; CHECK-NEXT: [[TMP17:%.*]] = and i32 [[TMP0]], 8
>> >> +; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 0
>> >> +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP18]], i32 44,
>> i32 88
>> >> ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]],
>> [[SUM4_NONCHR_V]]
>> >> -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP17]], i32
>> [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
>> >> +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP16]], i32
>> [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[TMP7]], [[BB0]] ], [
>> [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
>> >> @@ -656,8 +656,8 @@ define i32 @test_chr_6(i32* %i, i32* %j, i32
>> %sum0) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[V1:%.*]] = and i32 [[I0]], 255
>> >> -; CHECK-NEXT: [[V2:%.*]] = icmp eq i32 [[V1]], 0
>> >> -; CHECK-NEXT: br i1 [[V2]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[V2_NOT:%.*]] = icmp eq i32 [[V1]], 0
>> >> +; CHECK-NEXT: br i1 [[V2_NOT]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: [[V3_NONCHR:%.*]] = and i32 [[I0]], 2
>> >> ; CHECK-NEXT: [[V4_NONCHR:%.*]] = icmp eq i32 [[V3_NONCHR]], 0
>> >> @@ -807,8 +807,8 @@ define i32 @test_chr_7_1(i32* %i, i32* %j, i32
>> %sum0) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[V9:%.*]] = and i32 [[J0]], 4
>> >> -; CHECK-NEXT: [[V10:%.*]] = icmp eq i32 [[V9]], 0
>> >> -; CHECK-NEXT: br i1 [[V10]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[V10_NOT:%.*]] = icmp eq i32 [[V9]], 0
>> >> +; CHECK-NEXT: br i1 [[V10_NOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> @@ -948,22 +948,22 @@ define i32 @test_chr_9(i32* %i, i32* %j) !prof
>> !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP5]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> ; CHECK: bb1.nonchr:
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP7]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[J]], align 4
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [
>> [[TMP0]], [[BB1_NONCHR]] ], [ [[TMP8]], [[BB2_NONCHR]] ]
>> >> -; CHECK-NEXT: ret i32 [[TMP9]]
>> >> +; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [
>> [[TMP0]], [[BB1_NONCHR]] ], [ [[TMP7]], [[BB2_NONCHR]] ]
>> >> +; CHECK-NEXT: ret i32 [[TMP8]]
>> >> ;
>> >> entry:
>> >> %0 = load i32, i32* %i
>> >> @@ -1029,25 +1029,25 @@ define i32 @test_chr_10(i32* %i, i32* %j)
>> !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP5]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> ; CHECK: bb1.nonchr:
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[J]], align 4
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP8]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[J]], align 4
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP7]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [
>> [[TMP6]], [[BB2_NONCHR]] ], [ [[TMP6]], [[BB1_NONCHR]] ]
>> >> -; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], 42
>> >> -; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], -99
>> >> -; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP10]], [[TMP11]]
>> >> -; CHECK-NEXT: ret i32 [[TMP12]]
>> >> +; CHECK-NEXT: [[TMP8:%.*]] = phi i32 [ [[TMP3]], [[BB0]] ], [
>> [[TMP5]], [[BB2_NONCHR]] ], [ [[TMP5]], [[BB1_NONCHR]] ]
>> >> +; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], 42
>> >> +; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], -99
>> >> +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP9]], [[TMP10]]
>> >> +; CHECK-NEXT: ret i32 [[TMP11]]
>> >> ;
>> >> entry:
>> >> %0 = load i32, i32* %i
>> >> @@ -1476,24 +1476,24 @@ define i32 @test_chr_16(i32* %i) !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP4]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB1_NONCHR]]
>> >> ; CHECK: bb1.nonchr:
>> >> ; CHECK-NEXT: [[V40_NONCHR:%.*]] = add i32 [[TMP0]], 44
>> >> -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 2
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0]], 2
>> >> +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
>> >> +; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label
>> [[BB2_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb2.nonchr:
>> >> ; CHECK-NEXT: [[V41_NONCHR:%.*]] = add i32 [[TMP0]], 99
>> >> ; CHECK-NEXT: call void @foo()
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[V40]], [[BB0]] ], [
>> [[V40_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = phi i32 [ [[V40]], [[BB0]] ], [
>> [[V40_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]
>> >> ; CHECK-NEXT: [[V42:%.*]] = phi i32 [ [[V41]], [[BB0]] ], [
>> [[V41_NONCHR]], [[BB2_NONCHR]] ], [ [[V40_NONCHR]], [[BB1_NONCHR]] ]
>> >> -; CHECK-NEXT: [[V43:%.*]] = add i32 [[V42]], [[TMP7]]
>> >> +; CHECK-NEXT: [[V43:%.*]] = add i32 [[V42]], [[TMP6]]
>> >> ; CHECK-NEXT: ret i32 [[V43]]
>> >> ;
>> >> entry:
>> >> @@ -1661,8 +1661,8 @@ define i32 @test_chr_18(i32* %i, i32 %sum0)
>> !prof !14 {
>> >> ; CHECK-NEXT: br i1 [[CMP4_NONCHR]], label [[BB2]], label
>> [[BB1_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb1.nonchr:
>> >> ; CHECK-NEXT: [[A1:%.*]] = and i32 [[LI]], 1
>> >> -; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A1]], 0
>> >> -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1]], i32
>> [[SUM0]], i32 [[SUM1]], !prof !16
>> >> +; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[A1]], 0
>> >> +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1_NOT]], i32
>> [[SUM0]], i32 [[SUM1]], !prof !16
>> >> ; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44
>> >> ; CHECK-NEXT: br label [[BB2]]
>> >> ; CHECK: bb2:
>> >> @@ -1744,18 +1744,18 @@ define i32 @test_chr_19(i32* %i, i32 %sum0)
>> !prof !14 {
>> >> ; CHECK-NEXT: br label [[BB3:%.*]]
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 255
>> >> -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label
>> [[BB0_NONCHR:%.*]], !prof !16
>> >> ; CHECK: bb0.nonchr:
>> >> -; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP0]], 1
>> >> -; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0
>> >> -; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[SUM0]], 85
>> >> -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP8]], i32
>> [[SUM0]], i32 [[TMP9]], !prof !16
>> >> -; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP0]], 8
>> >> -; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0
>> >> -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP11]], i32 44,
>> i32 88
>> >> +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 1
>> >> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
>> >> +; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM0]], 85
>> >> +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP7]], i32
>> [[SUM0]], i32 [[TMP8]], !prof !16
>> >> +; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP0]], 8
>> >> +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
>> >> +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP10]], i32 44,
>> i32 88
>> >> ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]],
>> [[SUM4_NONCHR_V]]
>> >> -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP8]], i32
>> [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
>> >> +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP7]], i32
>> [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
>> >> ; CHECK-NEXT: br label [[BB3]]
>> >> ; CHECK: bb3:
>> >> ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [
>> [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
>> >> @@ -1842,8 +1842,8 @@ define i32 @test_chr_20(i32* %i, i32 %sum0, i1
>> %j) !prof !14 {
>> >> ; CHECK: entry.split.nonchr:
>> >> ; CHECK-NEXT: [[V8:%.*]] = add i32 [[SUM0]], 43
>> >> ; CHECK-NEXT: [[V3:%.*]] = and i32 [[I0]], 2
>> >> -; CHECK-NEXT: [[V4:%.*]] = icmp eq i32 [[V3]], 0
>> >> -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4]], i32
>> [[SUM0]], i32 [[V8]], !prof !16
>> >> +; CHECK-NEXT: [[V4_NOT:%.*]] = icmp eq i32 [[V3]], 0
>> >> +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4_NOT]], i32
>> [[SUM0]], i32 [[V8]], !prof !16
>> >> ; CHECK-NEXT: [[V6_NONCHR:%.*]] = and i32 [[I0]], 4
>> >> ; CHECK-NEXT: [[V5_NONCHR:%.*]] = icmp eq i32 [[V6_NONCHR]], 0
>> >> ; CHECK-NEXT: [[V9_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44
>> >> @@ -2328,7 +2328,7 @@ define i64 @test_chr_23(i64 %v0) !prof !14 {
>> >> ; CHECK-LABEL: @test_chr_23(
>> >> ; CHECK-NEXT: entry:
>> >> ; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[V0:%.*]], 50
>> >> -; CHECK-NEXT: [[V10:%.*]] = icmp ne i64 [[TMP0]], -50
>> >> +; CHECK-NEXT: [[V10_NOT:%.*]] = icmp eq i64 [[TMP0]], -50
>> >> ; CHECK-NEXT: ret i64 99
>> >> ;
>> >> entry:
>> >>
>> >> diff --git a/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll
>> b/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll
>> >> index 3439830d6265..60a6ca0d6379 100644
>> >> --- a/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll
>> >> +++ b/llvm/test/Transforms/SimplifyCFG/merge-cond-stores.ll
>> >> @@ -42,9 +42,9 @@ end:
>> >> define void @test_simple_commuted(i32* %p, i32 %a, i32 %b) {
>> >> ; CHECK-LABEL: @test_simple_commuted(
>> >> ; CHECK-NEXT: entry:
>> >> -; CHECK-NEXT: [[X1:%.*]] = icmp eq i32 [[A:%.*]], 0
>> >> +; CHECK-NEXT: [[X1_NOT:%.*]] = icmp eq i32 [[A:%.*]], 0
>> >> ; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B:%.*]], 0
>> >> -; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[X1]], [[X2]]
>> >> +; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[X1_NOT]], [[X2]]
>> >> ; CHECK-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label
>> [[TMP2:%.*]]
>> >> ; CHECK: 1:
>> >> ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = zext i1 [[X2]] to i32
>> >> @@ -274,13 +274,13 @@ define i32 @test_diamond_simple(i32* %p, i32*
>> %q, i32 %a, i32 %b) {
>> >> ; CHECK-NEXT: [[Z2:%.*]] = select i1 [[X1]], i32 [[B:%.*]], i32 0
>> >> ; CHECK-NEXT: [[X2:%.*]] = icmp eq i32 [[B]], 0
>> >> ; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[A]], [[B]]
>> >> -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
>> >> -; CHECK-NEXT: br i1 [[TMP1]], label [[TMP3:%.*]], label
>> [[TMP2:%.*]]
>> >> -; CHECK: 2:
>> >> +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP0]], 0
>> >> +; CHECK-NEXT: br i1 [[DOTNOT]], label [[TMP2:%.*]], label
>> [[TMP1:%.*]]
>> >> +; CHECK: 1:
>> >> ; CHECK-NEXT: [[SIMPLIFYCFG_MERGE:%.*]] = select i1 [[X2]], i32
>> [[Z2]], i32 1
>> >> ; CHECK-NEXT: store i32 [[SIMPLIFYCFG_MERGE]], i32* [[P:%.*]],
>> align 4
>> >> -; CHECK-NEXT: br label [[TMP3]]
>> >> -; CHECK: 3:
>> >> +; CHECK-NEXT: br label [[TMP2]]
>> >> +; CHECK: 2:
>> >> ; CHECK-NEXT: [[Z4:%.*]] = select i1 [[X2]], i32 [[Z2]], i32 3
>> >> ; CHECK-NEXT: ret i32 [[Z4]]
>> >> ;
>> >>
>> >>
>> >>
>> >> _______________________________________________
>> >> llvm-commits mailing list
>> >> llvm-commits at lists.llvm.org
>> >> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>>
>
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