[PATCH] D80802: [RISCV] Upgrade RVV MC to v0.9.

[Ferran Pallarès Roca via Phabricator via llvm-commits]

fpallares added a comment.

Thanks for the update @HsiangKai.

I've noticed that we aren't handling the exceptions that state that the `V0` constraint shouldn't be enforced for instructions that generate masks or for reductions.

For instance the following (valid) instructions are rejected:

  vmslt.vv v0, v2, v3, v0.t

  vredsum.vs v0, v1, v2, v0.t



================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:776
     }
-    return "";
+    llvm_unreachable("Unknown SEW.");
   }
----------------
evandro wrote:
> I'd rather the first case be the `default` case and that it would call `llvm_unreachabe()` instead.
I believe the LLVM Coding Standards recommend against `default` labels in switches over enums:

> -Wswitch warns if a switch, without a default label, over an enumeration does not cover every enumeration value. If you write a default label on a fully covered switch over an enumeration then the -Wswitch warning won’t fire when new elements are added to that enumeration.


See https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations .


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https://reviews.llvm.org/D80802