[PATCH] D84548: [AArch64][SVE] Add lowering for llvm fceil

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12137
                     AArch64CC::LAST_ACTIVE);
+  case Intrinsic::aarch64_sve_frintp:
+    return combineSVEPredIntrinsic(AArch64ISD::FRINTP_PRED, N, DAG);
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As suggested by Eli you only need to implement the FRINTP_PRED variant, which doesn't set any expectation on the result of inactive lanes.  Doing this means the intrinsics can remain untouched.

FYI: I'm in the process of converting the last few remaining instances of _MERGE_OP1 nodes (only the shifts and max/min remain) because we have no real need for them as yet and I'm trying to ensure we don't tie the register allocator's hands when code generating normal IR.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84548/new/

https://reviews.llvm.org/D84548