[PATCH] D66004: [WIP][X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 280728.
RKSimon added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66004/new/

https://reviews.llvm.org/D66004

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/avg.ll
  llvm/test/CodeGen/X86/avx-trunc.ll
  llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll
  llvm/test/CodeGen/X86/bitcast-setcc-128.ll
  llvm/test/CodeGen/X86/buildvec-extract.ll
  llvm/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/test/CodeGen/X86/combine-fcopysign.ll
  llvm/test/CodeGen/X86/combine-shl.ll
  llvm/test/CodeGen/X86/haddsub-shuf.ll
  llvm/test/CodeGen/X86/inline-asm-x-i128.ll
  llvm/test/CodeGen/X86/insert-into-constant-vector.ll
  llvm/test/CodeGen/X86/insertelement-shuffle.ll
  llvm/test/CodeGen/X86/known-signbits-vector.ll
  llvm/test/CodeGen/X86/load-partial.ll
  llvm/test/CodeGen/X86/load-slice.ll
  llvm/test/CodeGen/X86/masked_expandload.ll
  llvm/test/CodeGen/X86/masked_load.ll
  llvm/test/CodeGen/X86/masked_store_trunc.ll
  llvm/test/CodeGen/X86/oddshuffles.ll
  llvm/test/CodeGen/X86/oddsubvector.ll
  llvm/test/CodeGen/X86/pmul.ll
  llvm/test/CodeGen/X86/pmulh.ll
  llvm/test/CodeGen/X86/pr29112.ll
  llvm/test/CodeGen/X86/pr44976.ll
  llvm/test/CodeGen/X86/pr46585.ll
  llvm/test/CodeGen/X86/promote-cmp.ll
  llvm/test/CodeGen/X86/psubus.ll
  llvm/test/CodeGen/X86/shrink_vmul.ll
  llvm/test/CodeGen/X86/shuffle-of-insert.ll
  llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
  llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
  llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
  llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
  llvm/test/CodeGen/X86/sse41.ll
  llvm/test/CodeGen/X86/test-shrink-bug.ll
  llvm/test/CodeGen/X86/trunc-subvector.ll
  llvm/test/CodeGen/X86/udiv_fix.ll
  llvm/test/CodeGen/X86/udiv_fix_sat.ll
  llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll
  llvm/test/CodeGen/X86/vec_insert-2.ll
  llvm/test/CodeGen/X86/vec_insert-3.ll
  llvm/test/CodeGen/X86/vec_insert-5.ll
  llvm/test/CodeGen/X86/vec_int_to_fp.ll
  llvm/test/CodeGen/X86/vec_set-6.ll
  llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
  llvm/test/CodeGen/X86/vector-pack-256.ll
  llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-mul.ll
  llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
  llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
  llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
  llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vector-trunc.ll
  llvm/test/CodeGen/X86/vector-zext.ll
  llvm/test/CodeGen/X86/vselect.ll
  llvm/test/CodeGen/X86/vshift-4.ll

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