[llvm] 3b21823 - [X86][SSE] combineX86ShufflesRecursively - move all Root node asserts to the same location. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-07-25T12:48:14+01:00
New Revision: 3b21823e4abb501ca0b0de7777493be56a11cb67

URL: https://github.com/llvm/llvm-project/commit/3b21823e4abb501ca0b0de7777493be56a11cb67
DIFF: https://github.com/llvm/llvm-project/commit/3b21823e4abb501ca0b0de7777493be56a11cb67.diff

LOG: [X86][SSE] combineX86ShufflesRecursively - move all Root node asserts to the same location. NFCI.

Minor tidyup for some upcoming shuffle combine improvements.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4dc68d469bba..24bc264df129 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35346,6 +35346,9 @@ static SDValue combineX86ShufflesRecursively(
   assert(RootMask.size() > 0 &&
          (RootMask.size() > 1 || (RootMask[0] == 0 && SrcOpIndex == 0)) &&
          "Illegal shuffle root mask");
+  assert(Root.getSimpleValueType().isVector() &&
+         "Shuffles operate on vector types!");
+  unsigned RootSizeInBits = Root.getSimpleValueType().getSizeInBits();
 
   // Bound the depth of our recursive combine because this is ultimately
   // quadratic in nature.
@@ -35361,9 +35364,6 @@ static SDValue combineX86ShufflesRecursively(
   if (!VT.isVector())
     return SDValue(); // Bail if we hit a non-vector.
 
-  assert(Root.getSimpleValueType().isVector() &&
-         "Shuffles operate on vector types!");
-  unsigned RootSizeInBits = Root.getSimpleValueType().getSizeInBits();
   assert(VT.getSizeInBits() == RootSizeInBits &&
          "Can only combine shuffles of the same vector register size.");