[PATCH] D83818: [AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv

[Jon Roelofs via Phabricator via llvm-commits]

jroelofs updated this revision to Diff 280467.
jroelofs added a comment.

Add mir tests for each of the affected instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83818/new/

https://reviews.llvm.org/D83818

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/fjcvtzs.mir
  llvm/test/CodeGen/AArch64/flag-mainpulation.mir


Index: llvm/test/CodeGen/AArch64/flag-mainpulation.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/flag-mainpulation.mir
@@ -0,0 +1,22 @@
+# RUN: llc -o - %s -mtriple=arm64-eabi -mattr=+jsconv -run-pass=legalizer
+
+## Check that cfinv, setf8, setf16, and rmif all read/write nzcv.
+
+...
+---
+name:            test_flags
+liveins:
+  - { reg: '$d0' }
+  - { reg: '$w0' }
+  - { reg: '$x0' }
+body:             |
+  bb.0:
+    liveins: $d0, $w0, $x0
+
+    CFINV implicit-def $nzcv, implicit $nzcv
+    SETF8 renamable $w0, implicit-def $nzcv, implicit $nzcv
+    SETF16 renamable $w0, implicit-def $nzcv, implicit $nzcv
+    RMIF renamable $x0, 0, 0, implicit-def $nzcv, implicit $nzcv
+    RET undef $lr, implicit killed $w0
+
+...
Index: llvm/test/CodeGen/AArch64/fjcvtzs.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/fjcvtzs.mir
@@ -0,0 +1,15 @@
+# RUN: llc -o - %s -mtriple=arm64-eabi -mattr=+jsconv -run-pass=legalizer
+
+...
+---
+name:            test_jcvt
+liveins:
+  - { reg: '$d0' }
+body:             |
+  bb.0:
+    liveins: $d0
+
+    renamable $w0 = FJCVTZS killed renamable $d0, implicit-def $nzcv
+    RET undef $lr, implicit killed $w0
+
+...
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1030,7 +1030,7 @@
 }
 
 // v8.3a floating point conversion for javascript
-let Predicates = [HasJS, HasFPARMv8] in
+let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in
 def FJCVTZS  : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
                                       "fjcvtzs",
                                       [(set GPR32:$Rd,
@@ -1039,7 +1039,7 @@
 } // HasJS, HasFPARMv8
 
 // v8.4 Flag manipulation instructions
-let Predicates = [HasFMI] in {
+let Predicates = [HasFMI], Defs = [NZCV], Uses = [NZCV] in {
 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
   let Inst{20-5} = 0b0000001000000000;
 }
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1939,6 +1939,7 @@
     : I<(outs), iops, asm, ops, "", []>,
       Sched<[WriteI, ReadI, ReadI]> {
   let Uses = [NZCV];
+  let Defs = [NZCV];
   bits<5> Rn;
   let Inst{31}    = sf;
   let Inst{30-15} = 0b0111010000000000;


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