[PATCH] D84500: [ARM] Added additional patterns to VABD instruction

[Meera Nakrani via Phabricator via llvm-commits]

MeeraN created this revision.
MeeraN added reviewers: SjoerdMeijer, dmgreen.
MeeraN created this object with visibility "All Users".
MeeraN created this object with edit policy "No One".
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.

Added additional patterns to VABD instruction so that it will be selected in place of VSUB then VABS.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84500

Files:
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-vabd.ll


Index: llvm/test/CodeGen/Thumb2/mve-vabd.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/mve-vabd.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc void @vabd_v4f32(float* nocapture readonly %x, float* nocapture readonly %y, float* noalias nocapture %z) {
+; CHECK-LABEL: vabd_v4f32
+; CHECK:       @ %bb.0: @ %entry
+; CHECK:       .LBB0_1: @ %vector.body
+; CHECK-NEXT:  @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:  vldrw.u32 q0, [r1], #16
+; CHECK-NEXT:  vldrw.u32 q1, [r0], #16
+; CHECK-NEXT:  vabd.f32 q0, q1, q0
+; CHECK-NEXT:  vstrb.8 q0, [r2], #16
+; CHECK-NEXT:  le lr, .LBB0_1
+; CHECK-NEXT:  @ %bb.2: @ %for.cond.cleanup
+; CHECK-NEXT:  pop	{r7, pc}
+entry:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds float, float* %x, i32 %index
+  %1 = bitcast float* %0 to <4 x float>*
+  %wide.load = load <4 x float>, <4 x float>* %1, align 4
+  %2 = getelementptr inbounds float, float* %y, i32 %index
+  %3 = bitcast float* %2 to <4 x float>*
+  %wide.load10 = load <4 x float>, <4 x float>* %3, align 4
+  %4 = fsub fast <4 x float> %wide.load, %wide.load10 
+  %5 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %4)
+  %6 = getelementptr inbounds float, float* %z, i32 %index
+  %7 = bitcast float* %6 to <4 x float>*
+  store <4 x float> %5, <4 x float>* %7, align 4
+  %index.next = add i32 %index, 4
+  %8 = icmp eq i32 %index.next, 1024
+  br i1 %8, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %vector.body
+  ret void
+}
+
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
+
Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -3699,6 +3699,10 @@
               (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
                              ARMVCCThen, (VTI.Pred VCCR:$mask),
                              (VTI.Vec MQPR:$inactive)))>;
+    def : Pat<(v8f16 (fabs (fsub (v8f16 MQPR:$Qm), (v8f16 MQPR:$Qn)))),
+          (Inst MQPR:$Qm, MQPR:$Qn)>;
+    def : Pat<(v4f32 (fabs (fsub (v4f32 MQPR:$Qm), (v4f32 MQPR:$Qn)))),
+          (Inst MQPR:$Qm, MQPR:$Qn)>;
   }
 }
 


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