[PATCH] D82239: RISC-V machine attribute to disable floating-point division and square root instructions in codegen

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In D82239#2124411 <https://reviews.llvm.org/D82239#2124411>, @vb000 wrote:

> Hi @jrtc27,
>
> `fdiv` and `fsqrt` are rarely used instructions for many applications, but are beasts in terms of HW area consumption. While most of the `F` extension needs incremental additions to core FPU, `fdiv` and `fsqrt` need separate blocks of HW. Often this special purpose HW (whose sole purpose is to support two rarely used instructions) is not worth it in embedded applications. So, it's often fine to emulate those two instructions. So, there's definite value in having this option.
>
> (Also, this is not implemented just because GCC has this. We need this option to use LLVM on an already taped-out chip. I'm just trying to make it easy to transition from GCC to LLVM for ourselves, as well for other who might find this useful.)


Ok, but I object to saying F is enabled. It’s not. What’s implemented is a subset of it. So what you really want is a non-standard extension Xfnodivsqrt or something. If F is in my arch string I can always use fdiv and fsqrt, and those shouldn’t trap (provided mstatus.FS is suitably set).


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