[PATCH] D81360: [PowerPC] Fix RM operands for some instructions

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.

Please also add tests for `mtfsb0` etc.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:1510
 // Set the float rounding mode.
-let Uses = [RM], Defs = [RM] in {
+let Defs = [RM] in {
 def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),
----------------
`int_ppc_setrnd` will **read** `FPSCR` which include `RM`, why we want to remove the use of it?


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:2919
 // to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
-let Uses = [RM], Defs = [RM] in {
+let Defs = [RM] in {
   def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
----------------
`mtfsb0 ` will only change `RM` when the bit is 30/31, which is actually in `SETRNDi`, `SETRND`.. So I think we should not always `Def` RM here? Maybe some `PatLeaf` to check bits and only set it with 30/31 bits?
Similar for `mtfsfi`, `mtfsf`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81360/new/

https://reviews.llvm.org/D81360