[llvm] cfe40ac - [VectorCombine] add tests for load vectorization; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-07-23T11:24:04-04:00
New Revision: cfe40acd161d2b8a38c0d99b7f82f50e0d1e77db

URL: https://github.com/llvm/llvm-project/commit/cfe40acd161d2b8a38c0d99b7f82f50e0d1e77db
DIFF: https://github.com/llvm/llvm-project/commit/cfe40acd161d2b8a38c0d99b7f82f50e0d1e77db.diff

LOG: [VectorCombine] add tests for load vectorization; NFC

Added: 
    llvm/test/Transforms/VectorCombine/X86/load.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/VectorCombine/X86/load.ll b/llvm/test/Transforms/VectorCombine/X86/load.ll
new file mode 100644
index 000000000000..d560f671cfc0
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/load.ll
@@ -0,0 +1,129 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define float @matching_fp_scalar(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_scalar(
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[P:%.*]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = load float, float* %p, align 16
+  ret float %r
+}
+
+define float @matching_fp_scalar_volatile(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_scalar_volatile(
+; CHECK-NEXT:    [[R:%.*]] = load volatile float, float* [[P:%.*]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = load volatile float, float* %p, align 16
+  ret float %r
+}
+
+define double @larger_fp_scalar(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @larger_fp_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast float* [[P:%.*]] to double*
+; CHECK-NEXT:    [[R:%.*]] = load double, double* [[BC]], align 16
+; CHECK-NEXT:    ret double [[R]]
+;
+  %bc = bitcast float* %p to double*
+  %r = load double, double* %bc, align 16
+  ret double %r
+}
+
+define float @smaller_fp_scalar(double* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @smaller_fp_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast double* [[P:%.*]] to float*
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[BC]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %bc = bitcast double* %p to float*
+  %r = load float, float* %bc, align 16
+  ret float %r
+}
+
+define float @matching_fp_vector(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_vector(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float>* [[P:%.*]] to float*
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[BC]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %bc = bitcast <4 x float>* %p to float*
+  %r = load float, float* %bc, align 16
+  ret float %r
+}
+
+define float @matching_fp_vector_gep0(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_vector_gep0(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[P:%.*]], i64 0, i64 0
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[GEP]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 0, i64 0
+  %r = load float, float* %gep, align 16
+  ret float %r
+}
+
+define float @nonmatching_int_vector(<2 x i64>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @nonmatching_int_vector(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <2 x i64>* [[P:%.*]] to float*
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[BC]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %bc = bitcast <2 x i64>* %p to float*
+  %r = load float, float* %bc, align 16
+  ret float %r
+}
+
+define double @less_aligned(double* align 4 dereferenceable(16) %p) {
+; CHECK-LABEL: @less_aligned(
+; CHECK-NEXT:    [[R:%.*]] = load double, double* [[P:%.*]], align 4
+; CHECK-NEXT:    ret double [[R]]
+;
+  %r = load double, double* %p, align 4
+  ret double %r
+}
+
+define float @matching_fp_scalar_small_deref(float* align 16 dereferenceable(15) %p) {
+; CHECK-LABEL: @matching_fp_scalar_small_deref(
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[P:%.*]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = load float, float* %p, align 16
+  ret float %r
+}
+
+define i64 @larger_int_scalar(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @larger_int_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float>* [[P:%.*]] to i64*
+; CHECK-NEXT:    [[R:%.*]] = load i64, i64* [[BC]], align 16
+; CHECK-NEXT:    ret i64 [[R]]
+;
+  %bc = bitcast <4 x float>* %p to i64*
+  %r = load i64, i64* %bc, align 16
+  ret i64 %r
+}
+
+define i8 @smaller_int_scalar(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @smaller_int_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float>* [[P:%.*]] to i8*
+; CHECK-NEXT:    [[R:%.*]] = load i8, i8* [[BC]], align 16
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %bc = bitcast <4 x float>* %p to i8*
+  %r = load i8, i8* %bc, align 16
+  ret i8 %r
+}
+
+define double @larger_fp_scalar_256bit_vec(<8 x float>* align 32 dereferenceable(32) %p) {
+; CHECK-LABEL: @larger_fp_scalar_256bit_vec(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <8 x float>* [[P:%.*]] to double*
+; CHECK-NEXT:    [[R:%.*]] = load double, double* [[BC]], align 32
+; CHECK-NEXT:    ret double [[R]]
+;
+  %bc = bitcast <8 x float>* %p to double*
+  %r = load double, double* %bc, align 32
+  ret double %r
+}