[PATCH] D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions

[luxufan via Phabricator via llvm-commits]

StephenFan created this revision.
StephenFan added reviewers: HsiangKai, asb.
Herald added subscribers: llvm-commits, evandro, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

This implements the assemble and disassemble support of RISCV Vector extension Zvlsseg instructions, base on the 0.9 spec version.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84416

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVSchedRocket32.td
  llvm/lib/Target/RISCV/RISCVSchedRocket64.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/ext.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/zvlsseg.s

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