[PATCH] D84359: [PowerPC] Add vector pair load/store instructions and vector pair register class

[Baptiste Saleil via Phabricator via llvm-commits]

bsaleil created this revision.
bsaleil added reviewers: PowerPC, nemanjai, amyk, lei, stefanp.
bsaleil added projects: LLVM, PowerPC.
Herald added subscribers: llvm-commits, steven.zhang, shchenz, kbarton, hiraditya.

This patch adds support for the `lxvp`, `lxvpx`, `plxvp`, `stxvp`, `stxvpx` and `pstxvp` instructions in the PowerPC backend. These instructions allow loading and storing VSX register pairs.
This patch also adds the `VSRp` register class definition required needed for these instructions.

Depends on D83722 <https://reviews.llvm.org/D83722>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84359

Files:
  llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
  llvm/utils/TableGen/CodeGenTarget.cpp

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