[PATCH] D84324: AMDGPU/GlobalISel: Lower G_FREM

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2737
+    auto Div =
+        MIRBuilder.buildInstr(TargetOpcode::G_FDIV, {Ty}, {Src0Reg, Src1Reg});
+    auto Floor = MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR, {Ty}, {Div});
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buildFDiv? These are all dropping the flags too


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2738
+        MIRBuilder.buildInstr(TargetOpcode::G_FDIV, {Ty}, {Src0Reg, Src1Reg});
+    auto Floor = MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR, {Ty}, {Div});
+    auto Mul = MIRBuilder.buildFMul(Ty, Floor, Src1Reg);
----------------
buildFFloor?


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2738
+        MIRBuilder.buildInstr(TargetOpcode::G_FDIV, {Ty}, {Src0Reg, Src1Reg});
+    auto Floor = MIRBuilder.buildInstr(TargetOpcode::G_FFLOOR, {Ty}, {Div});
+    auto Mul = MIRBuilder.buildFMul(Ty, Floor, Src1Reg);
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arsenm wrote:
> buildFFloor?
Is this a correct handling of frem? The AMDGPU dag expansion uses ISD::FTRUNC, but I'm not sure that was ever correct


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84324/new/

https://reviews.llvm.org/D84324