[PATCH] D84312: AArch64: use "LBB-_func" entries in 32-bit jump tables for MachO

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

MachO has only 24-bits for relocation addends, which is too small to span a semi-reasonable sized function. This means jump table lowering has to be careful about two things:

- Any pc-relative address should be to a linker-visible symbol so the addend is 0. This was fixed previously by making the actual jump table symbol linker-private.
- The entries, "LBB-x", must be resolved at compile-time.

This implements the second point by making the base the function address itself on MachO targets. However, it only applies to MachO because it is a less efficient system overall (requiring the function address base to be materialized separately).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84312

Files:
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
  llvm/lib/Target/AArch64/AArch64ExpandHardenedPseudos.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64e-jump-table-hardening.ll
  llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
  llvm/test/CodeGen/AArch64/arm64e-jump-table-hardening.ll
  llvm/test/CodeGen/AArch64/jti-correct-datatype.mir
  llvm/test/CodeGen/AArch64/jump-table-compress.mir
  llvm/test/CodeGen/AArch64/jump-table.ll

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