[PATCH] D84308: [PowerPC] Retrieve the offset from load/store if it stores to stack slots
Qing Shan Zhang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 22 04:23:42 PDT 2020
steven.zhang created this revision.
steven.zhang added reviewers: jsji, qiucf, jasonliu, PowerPC.
Herald added subscribers: shchenz, wuzish, dexonsmith, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.
Scheduler will try to retrieve the offset and base addr to determine if two loads/stores are disjoint memory access. PowerPC failed to handle this for frame index which will bring extra memory dependency for loads/stores. See.
SU(15): STW %7:gprc, 28, %fixed-stack.0 :: (store 4 into %fixed-stack.0 + 28)
# preds left : 1
# succs left : 2
# rdefs left : 0
Latency : 1
Depth : 1
Height : 7
Predecessors:
SU(0): Data Latency=1 Reg=%7
Successors:
SU(17): Ord Latency=1 Memory
SU(16): Ord Latency=1 Memory
Pressure Diff : GPRC 1 SPILLTOVSRRC 1 SPILLTOVSRRC_with_VFRC 1 F4RC_with_SPILLTOVSRRC 1 VSSRC_with_SPILLTOVSRRC 1
Single Issue : false;
SU(16): %8:gprc = LWZ 84, %fixed-stack.0 :: (dereferenceable load 4 from %ir.arrayidx_b + 4, align 8)
# preds left : 8
# succs left : 1
# rdefs left : 0
Latency : 1
Depth : 2
Height : 6
Predecessors:
SU(15): Ord Latency=1 Memory #<--- Extra dependency which is not needed.
SU(14): Ord Latency=1 Memory
SU(13): Ord Latency=1 Memory
SU(12): Ord Latency=1 Memory
SU(11): Ord Latency=1 Memory
SU(10): Ord Latency=1 Memory
SU(9): Ord Latency=1 Memory
SU(8): Ord Latency=1 Memory
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D84308
Files:
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
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