[PATCH] D84044: [AArch64][SVE] Add missing unwind info for SVE registers.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

In D84044#2163137 <https://reviews.llvm.org/D84044#2163137>, @efriedma wrote:

> I'm confused by the stack layout involved here.  SVE registers should never be callee-save.  The ABI says we're only supposed to save the low 64 bits.


Just in case you were looking at the wrong version of the spec, https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#scalable-vector-registers contains the sections for SVE.

>From 6.1.3:

> If a subroutine takes at least one argument in scalable vector registers or scalable predicate registers, or if it is a function that returns results in such registers, it must ensure that the entire contents of z8-z23 are preserved across the call

The tests above have the `aarch64_sve_vector_pcs` calling convention annotation to enforce the SVE ABI for these functions, because they otherwise don't take or return any values. e.g.

  define aarch64_sve_vector_pcs void @save_restore_pregs_sve() { entry: unreachable }


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