[PATCH] D83986: GlobalISel: Define InvalidRegBankID enum value

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 279385.
arsenm added a comment.

Make enum unsigned to match getID


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83986/new/

https://reviews.llvm.org/D83986

Files:
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/utils/TableGen/RegisterBankEmitter.cpp


Index: llvm/utils/TableGen/RegisterBankEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -131,9 +131,12 @@
   // <Target>RegisterBankInfo.h
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n"
-     << "enum {\n";
+     << "enum : unsigned {\n";
+
+  OS << "InvalidRegBankID = ~0u,\n";
+  unsigned ID = 0;
   for (const auto &Bank : Banks)
-    OS << "  " << Bank.getEnumeratorName() << ",\n";
+    OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
   OS << "  NumRegisterBanks,\n"
      << "};\n"
      << "} // end namespace " << TargetName << "\n"
Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3303,10 +3303,10 @@
     AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 }
 
-static int regBankBoolUnion(int RB0, int RB1) {
-  if (RB0 == -1)
+static unsigned regBankBoolUnion(unsigned RB0, unsigned RB1) {
+  if (RB0 == AMDGPU::InvalidRegBankID)
     return RB1;
-  if (RB1 == -1)
+  if (RB1 == AMDGPU::InvalidRegBankID)
     return RB0;
 
   // vcc, vcc -> vcc
@@ -3414,8 +3414,7 @@
   //
   // TODO: There are additional exec masking dependencies to analyze.
   if (MI.getOpcode() == TargetOpcode::G_PHI) {
-    // TODO: Generate proper invalid bank enum.
-    int ResultBank = -1;
+    unsigned ResultBank = AMDGPU::InvalidRegBankID;
     Register DstReg = MI.getOperand(0).getReg();
 
     // Sometimes the result may have already been assigned a bank.
@@ -3437,7 +3436,7 @@
       ResultBank = regBankBoolUnion(ResultBank, OpBank);
     }
 
-    assert(ResultBank != -1);
+    assert(ResultBank != AMDGPU::InvalidRegBankID);
 
     unsigned Size = MRI.getType(DstReg).getSizeInBits();
 
@@ -3466,9 +3465,9 @@
       const RegisterBank *DstBank
         = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
 
-      unsigned TargetBankID = -1;
-      unsigned BankLHS = -1;
-      unsigned BankRHS = -1;
+      unsigned TargetBankID = AMDGPU::InvalidRegBankID;
+      unsigned BankLHS = AMDGPU::InvalidRegBankID;
+      unsigned BankRHS = AMDGPU::InvalidRegBankID;
       if (DstBank) {
         TargetBankID = DstBank->getID();
         if (DstBank == &AMDGPU::VCCRegBank) {


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