[PATCH] D83357: [llvm][sve] Reg + Imm addressing mode for ld1ro.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli updated this revision to Diff 279347.
fpetrogalli marked 2 inline comments as done.
fpetrogalli added a comment.

Rename variables in tablegen patterns.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83357/new/

https://reviews.llvm.org/D83357

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D83357.279347.patch
Type: text/x-patch
Size: 9520 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200721/3e06f387/attachment-0001.bin>