[PATCH] D77251: [llvm][CodeGen] Addressing modes for SVE ldN.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4731
 /// EVT.
+template <unsigned NumVec>
 static EVT getPackedVectorTypeFromPredicateType(LLVMContext &Ctx, EVT PredVT) {
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Why is this a template argument instead of a regular argument with default = 1?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4742
   EVT ScalarVT = EVT::getIntegerVT(Ctx, AArch64::SVEBitsPerBlock / EC.Min);
-  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC);
+  //  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC);
+  EVT MemVT = EVT::getVectorVT(Ctx, ScalarVT, EC * NumVec);
----------------
remove line?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:4768
     return cast<VTSDNode>(Root->getOperand(4))->getVT();
+  case AArch64ISD::SVE_LD2_MERGE_ZERO:
+    return getPackedVectorTypeFromPredicateType<2>(
----------------
How come that ST2..ST4 are not covered here?


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll:452
+; CHECK-NEXT: ret
+%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 16
+%base_ptr = bitcast <vscale x 2 x i64>* %base to i64 *
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nit: when testing these pairs, can you at least make sure to test the min/max values?


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+reg-addr-mode.ll:9
+%addr2 = getelementptr i8, i8 *  %addr, i64 %a
+%res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %gp, i8 *%addr2)
+ret <vscale x 32 x i8> %res
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nit: s/gp/pg/ (in both tests)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D77251/new/

https://reviews.llvm.org/D77251