[PATCH] D83569: [PowerPC] Fix the killed flag in mi-peephole pass

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang updated this revision to Diff 279232.
ZhangKang added a comment.

Remove the dump code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83569/new/

https://reviews.llvm.org/D83569

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
  llvm/test/CodeGen/PowerPC/mi-peephole.mir


Index: llvm/test/CodeGen/PowerPC/mi-peephole.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/mi-peephole.mir
+++ llvm/test/CodeGen/PowerPC/mi-peephole.mir
@@ -31,7 +31,7 @@
   ; CHECK: bb.0.entry:
   ; CHECK:   %1:g8rc = COPY $x4
   ; CHECK:   %0:g8rc = COPY $x3
-  ; CHECK:   %3:g8rc = RLDIC %1, 2, 30
+  ; CHECK:   %3:g8rc = RLDIC killed %1, 2, 30
   ; CHECK:   $x3 = COPY %3
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
 ...
Index: llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
+++ llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
@@ -51,4 +51,4 @@
 #
 # CHECK-PASS-NOT:     %2:g8rc = RLDICL killed %1, 0, 32
 # CHECK-PASS-NOT:     %3:g8rc = RLDICR %2, 2, 61
-# CHECK-PASS:     %3:g8rc = RLDIC %1, 2, 30
+# CHECK-PASS:     %3:g8rc = RLDIC killed %1, 2, 30
Index: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -1556,6 +1556,33 @@
   MI.getOperand(2).setImm(NewSH);
   MI.getOperand(3).setImm(NewMB);
 
+  if (SrcMI->getOperand(1).isKill()) {
+    MI.getOperand(1).setIsKill(true);
+    SrcMI->getOperand(1).setIsKill(false);
+  }
+
+  // FIXME: fix kill/dead flag if MI and *SrcMI are not in same basic block.
+  if (SrcMI->getParent() == MI.getParent()) {
+    // Check if reg is killed between MI and *SrcMI.
+    auto IsKilledFor = [&](unsigned Reg) {
+      MachineBasicBlock::const_reverse_iterator It = MI;
+      MachineBasicBlock::const_reverse_iterator E = *SrcMI;
+      It++;
+      for (; It != E; ++It) {
+        if (It->killsRegister(Reg))
+          return true;
+      }
+      return false;
+    };
+
+    if (SrcMI->getOperand(0).isKill() ||
+        IsKilledFor(SrcMI->getOperand(0).getReg()))
+      TII->fixupIsDeadOrKill(*SrcMI, MI, SrcMI->getOperand(0).getReg());
+
+    if (MI.getOperand(1).isKill() || IsKilledFor(MI.getOperand(1).getReg()))
+      TII->fixupIsDeadOrKill(*SrcMI, MI, SrcMI->getOperand(1).getReg());
+  }
+
   LLVM_DEBUG(dbgs() << "To: ");
   LLVM_DEBUG(MI.dump());
   NumRotatesCollapsed++;


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