[PATCH] D84166: AMDGPU: Simplify f16 to i64 custom lowering

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: foad, arsenm.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

Range that f16 can represent fits into i32.
Lower as f16->i32->i64 instead of f16->f32->i64
since f32->i64 has long expansion.


https://reviews.llvm.org/D84166

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
  llvm/test/CodeGen/AMDGPU/fptoui.f16.ll


Index: llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
+++ llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
@@ -105,7 +105,6 @@
 
 ; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i64
 ; GCN: buffer_load_dword
-; GCN: v_cvt_f32_f16_e32
 ; SI: v_cvt_f32_f16_e32
 ; VI: v_cvt_f32_f16_sdwa
 ; GCN: s_endpgm
Index: llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
+++ llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
@@ -105,7 +105,6 @@
 
 ; GCN-LABEL: {{^}}fptosi_v2f16_to_v2i64
 ; GCN: buffer_load_dword
-; GCN: v_cvt_f32_f16_e32
 ; SI: v_cvt_f32_f16_e32
 ; VI: v_cvt_f32_f16_sdwa
 ; GCN: s_endpgm
Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2701,11 +2701,8 @@
   if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
     SDLoc DL(Op);
 
-    SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
-    SDValue FpToInt32 =
-        DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
-
-    return FpToInt32;
+    SDValue FpToInt32 = DAG.getNode(Op.getOpcode(), DL, MVT::i32, Src);
+    return DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, FpToInt32);
   }
 
   if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
@@ -2724,11 +2721,8 @@
   if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) {
     SDLoc DL(Op);
 
-    SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);
-    SDValue FpToInt32 =
-        DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);
-
-    return FpToInt32;
+    SDValue FpToUInt32 = DAG.getNode(Op.getOpcode(), DL, MVT::i32, Src);
+    return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, FpToUInt32);
   }
 
   if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)


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