[PATCH] D81360: [PowerPC] Fix RM operands for some instructions
Zhang Kang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 18 23:56:21 PDT 2020
ZhangKang added a comment.
In D81360#2159250 <https://reviews.llvm.org/D81360#2159250>, @jsji wrote:
> Also why this depends on D76042 <https://reviews.llvm.org/D76042>?
The patch D76042 <https://reviews.llvm.org/D76042> will remove the redundant the implicit operands in ppc-early-ret pass.
Below code is from the origin case `test/CodeGen/PowerPC/early-ret.mir`.
109 ; CHECK: BCLR killed renamable $cr0eq, implicit $lr, implicit $rm, implicit $lr, implicit $rm, implicit killed $v2
110 ; CHECK: bb.1.entry:
111 ; CHECK: renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
112 ; CHECK: BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
The patch D76042 <https://reviews.llvm.org/D76042> will fix the redundant implicit in line 109, you can see the line 112 is right. In fact, here line 112 is right,
because we have forgotten to set 'Uses = [LR, RM]', this is what this patch does. So I set this patch depends on D76042 <https://reviews.llvm.org/D76042>, or we will
see the line 112 will be wrong after fix the 'RM' flag.
1526 let isReturn = 1, Uses = [LR, RM] in
1527 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1528 "bclr 12, $bi, 0", IIC_BrB, []>;
1529 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1530 "bclr 4, $bi, 0", IIC_BrB, []>;
Repository:
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CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81360/new/
https://reviews.llvm.org/D81360
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