[PATCH] D84101: [ARM] Add predicated add reduction patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samparker, efriedma, simon_tatham, ostannard.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.

Given a vecreduce.add(select(p, x, 0)), we can convert that to a predicated vaddv, as the negative value for the select is the identity value, a zero. That is what this patch does for the vaddv, vaddva, vaddlv and vaddlva instruction, copying the existing patterns to also handle predication through a select.


https://reviews.llvm.org/D84101

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll

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