[PATCH] D84041: [AArch64][SVE] Fix PCS for functions taking/returning scalable types.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: efriedma, paulwalker-arm, david-arm.
Herald added subscribers: danielkiss, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

The default calling convention needs to save/restore the SVE callee
saves according to the SVE PCS when the function takes or returns
scalable types, even when the `aarch64_sve_vector_pcs` CC is not
specified for the function.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84041

Files:
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/test/CodeGen/AArch64/sve-calling-convention.ll


Index: llvm/test/CodeGen/AArch64/sve-calling-convention.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-calling-convention.ll
+++ llvm/test/CodeGen/AArch64/sve-calling-convention.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=finalize-isel < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -stop-after=prologepilog < %s 2>%t | FileCheck %s --check-prefix=CHECKCSR
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
@@ -123,3 +124,25 @@
   %res = call <vscale x 4 x i1> @sve_signature_pred(<vscale x 4 x i1> %arg2, <vscale x 4 x i1> %arg1)
   ret <vscale x 4 x i1> %res
 }
+
+; Test that functions returning or taking SVE arguments use the correct
+; callee-saved set when using the default C calling convention (as opposed
+; to aarch64_sve_vector_pcs)
+
+; CHECKCSR-LABEL: name: sve_signature_vec_ret_callee
+; CHECKCSR: callee-saved-register: '$z8'
+; CHECKCSR: callee-saved-register: '$p4'
+; CHECKCSR: RET_ReallyLR
+define <vscale x 4 x i32> @sve_signature_vec_ret_callee() nounwind {
+  call void asm sideeffect "nop", "~{z8},~{p4}"()
+  ret <vscale x 4 x i32> zeroinitializer
+}
+
+; CHECKCSR-LABEL: name: sve_signature_vec_arg_callee
+; CHECKCSR: callee-saved-register: '$z8'
+; CHECKCSR: callee-saved-register: '$p4'
+; CHECKCSR: RET_ReallyLR
+define void @sve_signature_vec_arg_callee(<vscale x 4 x i32> %v) nounwind {
+  call void asm sideeffect "nop", "~{z8},~{p4}"()
+  ret void
+}
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -40,6 +40,22 @@
   AArch64_MC::initLLVMToCVRegMapping(this);
 }
 
+static bool needsSVECallingConvention(const MachineFunction *MF) {
+  const Function &F = MF->getFunction();
+  if (F.getCallingConv() == CallingConv::AArch64_SVE_VectorCall)
+    return true;
+
+  if (isa<ScalableVectorType>(F.getReturnType()))
+    return true;
+
+  if (any_of(F.args(), [](const Argument &Arg) {
+        return isa<ScalableVectorType>(Arg.getType());
+      }))
+    return true;
+
+  return false;
+}
+
 const MCPhysReg *
 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
@@ -62,7 +78,7 @@
     return CSR_Win_AArch64_AAPCS_SaveList;
   if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
     return CSR_AArch64_AAVPCS_SaveList;
-  if (MF->getFunction().getCallingConv() == CallingConv::AArch64_SVE_VectorCall)
+  if (needsSVECallingConvention(MF))
     return CSR_AArch64_SVE_AAPCS_SaveList;
   if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
           ->supportSwiftError() &&


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