[PATCH] D78285: [TableGen] Report an error instead of asserting

[Jay Foad via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1cfb207737cc: [TableGen] Report an error instead of asserting (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78285/new/

https://reviews.llvm.org/D78285

Files:
  llvm/test/TableGen/RegisterClass.td
  llvm/utils/TableGen/CodeGenRegisters.cpp


Index: llvm/utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenRegisters.cpp
+++ llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -743,6 +743,8 @@
       TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) {
   GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
   std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
+  if (TypeList.empty())
+    PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
   for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
     Record *Type = TypeList[i];
     if (!Type->isSubClassOf("ValueType"))
@@ -751,7 +753,6 @@
                           "' does not derive from the ValueType class!");
     VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes()));
   }
-  assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
 
   // Allocation order 0 is the full set. AltOrders provides others.
   const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
Index: llvm/test/TableGen/RegisterClass.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/RegisterClass.td
@@ -0,0 +1,7 @@
+// RUN: not llvm-tblgen -gen-register-bank -I %p/../../include %s 2>&1 | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def MyTarget : Target;
+def R0 : Register<"r0">;
+def ClassA : RegisterClass<"MyTarget", [], 32, (add R0)>; // CHECK: [[@LINE]]:1: error: RegTypes list must not be empty!


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