[PATCH] D84010: AMDGPU/GlobalISel: Legalize s16->s64 G_FPTOSI/G_FPTOUI

Fri Jul 17 03:28:07 PDT 2020

foad added inline comments.

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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir:598-633
+    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2139095040
+    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
+    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[FPEXT]], [[C]]
+    ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
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This expansion is huge! How about implementing it as: fpext from f16 to f32, then fptosi/fptoui from f32 to i32 (you know this will be in range because the range of f16 is only about +/-65536), then sext/zext from i32 to i64?

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84010/new/

https://reviews.llvm.org/D84010