[PATCH] D83986: GlobalISel: Define InvalidRegBankID enum value

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: qcolombet, dsanders, aemerson, paquette, aditya_nandakumar.
Herald added subscribers: kerbowa, hiraditya, rovka, nhaehnle, wdng, jvesely.
Herald added a project: LLVM.

https://reviews.llvm.org/D83986

Files:
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/utils/TableGen/RegisterBankEmitter.cpp


Index: llvm/utils/TableGen/RegisterBankEmitter.cpp
===================================================================
--- llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -132,6 +132,8 @@
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n"
      << "enum {\n";
+
+  OS << "InvalidRegBankID = -1,\n";
   for (const auto &Bank : Banks)
     OS << "  " << Bank.getEnumeratorName() << ",\n";
   OS << "  NumRegisterBanks,\n"
Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3305,9 +3305,9 @@
 }
 
 static int regBankBoolUnion(int RB0, int RB1) {
-  if (RB0 == -1)
+  if (RB0 == AMDGPU::InvalidRegBankID)
     return RB1;
-  if (RB1 == -1)
+  if (RB1 == AMDGPU::InvalidRegBankID)
     return RB0;
 
   // vcc, vcc -> vcc
@@ -3415,8 +3415,7 @@
   //
   // TODO: There are additional exec masking dependencies to analyze.
   if (MI.getOpcode() == TargetOpcode::G_PHI) {
-    // TODO: Generate proper invalid bank enum.
-    int ResultBank = -1;
+    int ResultBank = AMDGPU::InvalidRegBankID;
     Register DstReg = MI.getOperand(0).getReg();
 
     // Sometimes the result may have already been assigned a bank.
@@ -3438,7 +3437,7 @@
       ResultBank = regBankBoolUnion(ResultBank, OpBank);
     }
 
-    assert(ResultBank != -1);
+    assert(ResultBank != AMDGPU::InvalidRegBankID);
 
     unsigned Size = MRI.getType(DstReg).getSizeInBits();
 
@@ -3467,9 +3466,9 @@
       const RegisterBank *DstBank
         = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
 
-      unsigned TargetBankID = -1;
-      unsigned BankLHS = -1;
-      unsigned BankRHS = -1;
+      unsigned TargetBankID = AMDGPU::InvalidRegBankID;
+      unsigned BankLHS = AMDGPU::InvalidRegBankID;
+      unsigned BankRHS = AMDGPU::InvalidRegBankID;
       if (DstBank) {
         TargetBankID = DstBank->getID();
         if (DstBank == &AMDGPU::VCCRegBank) {


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D83986.278601.patch
Type: text/x-patch
Size: 2087 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200716/70df592f/attachment.bin>