[llvm] 9adf746 - [X86] Add test case for PR46455.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-07-16T11:06:55-07:00
New Revision: 9adf7461f721170419058684a8d3f9228d641d59

URL: https://github.com/llvm/llvm-project/commit/9adf7461f721170419058684a8d3f9228d641d59
DIFF: https://github.com/llvm/llvm-project/commit/9adf7461f721170419058684a8d3f9228d641d59.diff

LOG: [X86] Add test case for PR46455.

Added: 
    llvm/test/CodeGen/X86/pr46455.ll

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 450927aaf5cc..8dfe7396699f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -44523,6 +44523,8 @@ static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG,
       isHorizontalBinOp(LHS, RHS, DAG, Subtarget, IsFadd))
     return DAG.getNode(HorizOpcode, SDLoc(N), VT, LHS, RHS);
 
+  // NOTE: isHorizontalBinOp may have changed LHS/RHS variables.
+
   return SDValue();
 }
 

diff  --git a/llvm/test/CodeGen/X86/pr46455.ll b/llvm/test/CodeGen/X86/pr46455.ll
new file mode 100644
index 000000000000..7f608fbfdf6d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr46455.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512vl,avx512bw,avx512dq | FileCheck %s
+
+define void @EntryModule(i8** %buffer_table) {
+; CHECK-LABEL: EntryModule:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    movq (%rdi), %rax
+; CHECK-NEXT:    movq 24(%rdi), %rcx
+; CHECK-NEXT:    vcmpneqps (%rax), %ymm0, %ymm0
+; CHECK-NEXT:    vandps {{.*}}(%rip){1to4}, %xmm0, %xmm1
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm3 = xmm1[3,1,2,3]
+; CHECK-NEXT:    vpaddd %xmm3, %xmm2, %xmm2
+; CHECK-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vmovd %xmm0, (%rcx)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+entry:
+  %i = bitcast i8** %buffer_table to <8 x float>**
+  %i1 = load <8 x float>*, <8 x float>** %i, align 8
+  %i6 = load <8 x float>, <8 x float>* %i1, align 16
+  %i7 = fcmp une <8 x float> %i6, zeroinitializer
+  %i8 = zext <8 x i1> %i7 to <8 x i32>
+  %i18 = getelementptr inbounds i8*, i8** %buffer_table, i64 3
+  %i19 = load i8*, i8** %i18, align 8
+  %shift = shufflevector <8 x i32> %i8, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %i20 = add nuw nsw <8 x i32> %shift, %i8
+  %shift13 = shufflevector <8 x i32> %i8, <8 x i32> undef, <8 x i32> <i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %i21 = add nuw nsw <8 x i32> %i20, %shift13
+  %shift14 = shufflevector <8 x i32> %i8, <8 x i32> undef, <8 x i32> <i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %i22 = add nuw nsw <8 x i32> %i21, %shift14
+  %i23 = extractelement <8 x i32> %i22, i32 0
+  %i24 = bitcast i8* %i19 to i32*
+  store i32 %i23, i32* %i24, align 8
+  ret void
+}