[PATCH] D83561: [ScheduleDAG] Move DBG_VALUEs after first term forward.
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 08:09:18 PDT 2020
fhahn updated this revision to Diff 278485.
fhahn added a comment.
In D83561#2153981 <https://reviews.llvm.org/D83561#2153981>, @jmorse wrote:
> Should be a matter of
>
> MI.getOperand(0).setReg(0)
>
>
> Operand zero is the variable location; zero / $noreg is used to indicate that there is no location for the variable. If it's not a register MachineOperand, the ChangeToRegister method would be needed.
Thanks, updated to use ChangeToRegister(0, false).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83561/new/
https://reviews.llvm.org/D83561
Files:
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/test/CodeGen/ARM/dbg-tcreturn.ll
Index: llvm/test/CodeGen/ARM/dbg-tcreturn.ll
===================================================================
--- llvm/test/CodeGen/ARM/dbg-tcreturn.ll
+++ llvm/test/CodeGen/ARM/dbg-tcreturn.ll
@@ -1,5 +1,4 @@
-; XFAIL: *
-; RUN: llc %s -o - -stop-after=finalize-isel -verify-machineinstr | FileCheck %s
+; RUN: llc %s -o - -stop-after=finalize-isel -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7-apple-ios7.0.0"
@@ -12,8 +11,8 @@
; CHECK-NEXT: %0:gpr = COPY $r0
; CHECK-NEXT: $r0 = COPY %0
; CHECK-NEXT: $r1 = COPY %1
-; CHECK-NEXT: TCRETURNdi &__divsi3, implicit $sp, implicit $r0, implicit $r1
; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !13, !DIExpression(), debug-location !16
+; CHECK-NEXT: TCRETURNdi &__divsi3, implicit $sp, implicit $r0, implicit $r1
define i32 @test(i32 %a1, i32 %a2) !dbg !5 {
entry:
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -1034,7 +1034,29 @@
}
InsertPos = Emitter.getInsertPos();
- return Emitter.getBlock();
+ // In some cases, DBG_VALUEs might be inserted after the first terminator,
+ // which results in an invalid MBB. If that happens, move the DBG_VALUEs
+ // before the first terminator.
+ MachineBasicBlock *InsertBB = Emitter.getBlock();
+ auto FirstTerm = InsertBB->getFirstTerminator();
+ if (FirstTerm != InsertBB->end()) {
+ assert(!FirstTerm->isDebugValue() &&
+ "first terminator cannot be a debug value");
+ for (MachineInstr &MI : make_early_inc_range(
+ make_range(std::next(FirstTerm), InsertBB->end()))) {
+ if (!MI.isDebugValue())
+ continue;
+
+ if (&MI == InsertPos)
+ InsertPos = std::prev(InsertPos->getIterator());
+
+ // The DBG_VALUE was referencing a value produced by a terminator. By
+ // moving the DBG_VALUE, the referenced value also needs invalidating.
+ MI.getOperand(0).ChangeToRegister(0, false);
+ MI.moveBefore(&*FirstTerm);
+ }
+ }
+ return InsertBB;
}
/// Return the basic block label.
Index: llvm/lib/CodeGen/MachineInstr.cpp
===================================================================
--- llvm/lib/CodeGen/MachineInstr.cpp
+++ llvm/lib/CodeGen/MachineInstr.cpp
@@ -147,6 +147,10 @@
setFlags(MI.Flags);
}
+void MachineInstr::moveBefore(MachineInstr *MovePos) {
+ MovePos->getParent()->splice(MovePos, getParent(), getIterator());
+}
+
/// getRegInfo - If this instruction is embedded into a MachineFunction,
/// return the MachineRegisterInfo object for the current function, otherwise
/// return null.
Index: llvm/include/llvm/CodeGen/MachineInstr.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineInstr.h
+++ llvm/include/llvm/CodeGen/MachineInstr.h
@@ -280,6 +280,9 @@
const MachineBasicBlock* getParent() const { return Parent; }
MachineBasicBlock* getParent() { return Parent; }
+ // Move the instruction before \p MovePos.
+ void moveBefore(MachineInstr *MovePos);
+
/// Return the function that contains the basic block that this instruction
/// belongs to.
///
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