[PATCH] D83948: [PowerPC] Custom lowering for funnel shifts
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 06:39:42 PDT 2020
foad marked 3 inline comments as done.
foad added inline comments.
Herald added a subscriber: wuzish.
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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:616-624
+ // PowerPC has better expansions for funnel shifts than the generic
+ // TargetLowering::expandFunnelShift.
+ if (Subtarget.has64BitSupport()) {
+ setOperationAction(ISD::FSHL, MVT::i64, Custom);
+ setOperationAction(ISD::FSHR, MVT::i64, Custom);
+ }
+ setOperationAction(ISD::FSHL, MVT::i32, Custom);
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This is just guesswork. I'm really not sure which types we should do this for, under what conditions.
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Comment at: llvm/test/CodeGen/PowerPC/funnel-shift.ll:31-43
+define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: fshl_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 5, 5, 26
+; CHECK-NEXT: subfic 6, 5, 64
+; CHECK-NEXT: sld 3, 3, 5
+; CHECK-NEXT: srd 4, 4, 6
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Can I pre-commit this new test case, and fshr_i64?
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Comment at: llvm/test/CodeGen/PowerPC/pr44183.ll:16-21
+; CHECK-NEXT: li r3, 4
+; CHECK-NEXT: ld r4, 16(r30)
+; CHECK-NEXT: ld r5, 8(r30)
+; CHECK-NEXT: subfic r29, r3, 64
+; CHECK-NEXT: rldicl r3, r5, 60, 4
+; CHECK-NEXT: sld r4, r4, r29
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This regressions seems to be caused by not constant folding based on the fact that r3 is known to be 4. Can anyone suggest how to fix it? Do I have to spot known constant shift amounts in PPCTargetLowering::LowerFunnelShift?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D83948/new/
https://reviews.llvm.org/D83948
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