[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR

Thu Jul 16 03:05:31 PDT 2020

RKSimon added inline comments.

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Comment at: llvm/test/CodeGen/PowerPC/funnel-shift.ll:22-24
+; CHECK-NEXT:    clrlwi 5, 5, 27
+; CHECK-NEXT:    srwi 4, 4, 1
+; CHECK-NEXT:    clrlwi 6, 6, 27
----------------
foad wrote:
> RKSimon wrote:
> > foad wrote:
> > > RKSimon wrote:
> > > > foad wrote:
> > > > > This is a slight regression. We need one more instruction overall because of the two clrlwi instructions to mask both normal and the inverted shift amounts.
> > > > Any luck with this?
> > > No. I think it would need a target-specific lowering to take advantage of the fact that shift by 32 is well defined on PowerPC. Can I leave this for a later patch, and/or could a PowerPC expert volunteer to help with it?
> > So we're not just missing a micro optimization we can add to the powerpc backend as part of this patch? @hfinkel Any suggestions?
> I can't think of a simple micro optimization that would help. For PowerPC it would be better to expand fshl(X, Y, Z) as `X << (Z & 31) | Y >> (32 - (Z & 31))` (where the right shift supports shifting by 32) which would be better than either the "before" or the "after" code shown in this diff.
Are you able to add the PPC custom lowering to this patch?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77152/new/

https://reviews.llvm.org/D77152