[PATCH] D68035: [PowerPC] Extend custom lower of vector truncate to handle wider input
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 15 15:17:07 PDT 2020
nemanjai added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:7166
+ EVT VecIdxTy =
+ DAG.getTargetLoweringInfo().getVectorIdxTy(DAG.getDataLayout());
+ EVT SrcEltVT = N1.getValueType().getVectorElementType();
----------------
I believe `DAG.getTargetLoweringInfo()` is just `*this` so we should be able to just call `getVectorIdxTy()` unqualified.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:7169
+ unsigned SplitNumElts = 128 / SrcEltVT.getSizeInBits();
+ EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), SrcEltVT, SplitNumElts);
+ Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1,
----------------
Isn't `SplitVT` just `SrcVT.getHalfNumVectorElementsVT(*DAG.getContext())`?
Seems that all of the definitions here can just be something like:
```
EVT VecIdxTy = getVectorIdxTy(DAG.getDataLayout());
EVT SplitVT = N1.getValueType().getHalfNumVectorElementsVT(*DAG.getContext());
unsigned SplitNumElts = SplitVT.getVectorNumElements();
```
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10208
isOperationCustom(N->getOpcode(), TrgVT) &&
- OpVT.getSizeInBits() <= 128 &&
+ OpVT.getSizeInBits() <= 256 &&
+ isPowerOf2_32(TrgVT.getVectorElementType().getSizeInBits()) &&
----------------
We check that the number of elements in the wide input is a power of 2 as well as that the target element type width is a power of 2.
What happens with something weird like `trunc <8 x i24> to <8 x i16>` (also, please add such a test case)?
================
Comment at: llvm/test/CodeGen/PowerPC/vec-trunc2.ll:21
+; CHECK: lvx v4, 0, r3
+; CHECK: vperm v2, v3, v2, v4
+; CHECK: blr
----------------
Please add a check that shows how we produced `v3`. Presumably this is a shift from `v2`?
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https://reviews.llvm.org/D68035/new/
https://reviews.llvm.org/D68035
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