[PATCH] D83730: [AMDGPU] Spill CSR VGPR which is reserved for SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:361
+  Optional<int> CSRSpillFI;
+  if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
+      isCalleeSavedReg(CSRegs, LaneVGPR)) {
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I think checking for isEntryFunction is redundant with checking for CSRegs. Why does this need to worry about calls? This will miss the tail call case.

Can you also comment this?


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Comment at: llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll:19
 
 define void @parent_func() #0 {
+  %alloca = alloca i32, align 4, addrspace(5)
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Can you also add a test that only has a tail call?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83730/new/

https://reviews.llvm.org/D83730